4
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF502 / IXDI502 / IXDN502
Unless otherwise noted, 4.5V ≤ V
CC
≤ 30V , Tj < 150
o
C
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. All specifications are for one channel.
Electrical Characteristics @ temperatures over -55
o
C to 125
o
C
(3)
V
IH
High input voltage
4.5V ≤ V
CC
≤ 15V
3.1 V
V
IL
Low input voltage
4.5V ≤ V
CC
≤ 15V
0.8 V
V
IN
Input voltage range -5 V
CC
+ 0.3 V
I
IN
Input current
0V ≤ V
IN
≤ V
CC
-10 10
µA
V
OH
High output voltage V
CC
- 0.025
V
V
OL
Low output voltage 0.025 V
R
OH
High state output
resistance
V
CC
= 15V
6
Ω
R
OL
Low state output
resistance
V
CC
= 15V
5
Ω
I
DC
Continuous output
current
1 A
t
R
Rise time C
LOAD
=1000pF V
CC
=15V 11 ns
t
F
Fall time C
LOAD
=1000pF V
CC
=15V 10 ns
t
ONDLY
On-time propagation
delay
C
LOAD
=1000pF V
CC
=15V
40 ns
t
OFFDLY
Off-time propagation
delay
C
LOAD
=1000pF V
CC
=15V
38 ns
V
CC
Power supply voltage 4.5 15 30 V
I
CC
Power supply current
V
IN
= 3.5V
V
IN
= 0V
V
IN
= + V
CC
1
0
3
40
40
mA
µA
µA
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
* The following notes are meant to define the conditions for the θ
J-A
, θ
J-C
and θ
J-S
values:
1) The θ
J-A
(typ) is defined as junction to ambient. The θ
J-A
of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the
resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards
and the values would be lower with forced convection. For the 6-Lead DFN package, the θ
J-A
value supposes the DFN package is
soldered on a PCB. The θ
J-A
(typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a low
thermal resistance to the die, it is easy to reduce the θ
J-A
by adding connected copper pads or traces on the PCB. These can reduce
the θ
J-A
(typ) to 125 °C/W easily, and potentially even lower. The θ
J-A
for DFN on PCB without heatsink or thermal management will
vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no
thermal management.
2) θ
J-C
(max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θ
J-C
values are generally not
published for the PDIP and SOIC packages. The θ
J-C
for the DFN packages are important to show the low thermal resistance from junction to
the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The θ
J-S
(typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.
The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the
U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFN package.
