ADP130 Data Sheet
Rev. C | Page 12 of 20
THEORY OF OPERATION
The ADP130 is a low dropout, linear regulator that uses an
advanced proprietary architecture to achieve low quiescent
current and high efficiency regulation. It also provides high
power supply rejection ratio (PSRR) and excellent line and load
transient response using a small 1 F ceramic output capacitor. The
device operates from a 2.3 V to 5.5 V bias rail and a 1.2 V to 3.6 V
input rail to provide up to 350 mA of output current. Supply
current in shutdown mode is typically less than 1 µA.
Internally, the ADP130 consists of a reference, an error ampli-
fier, a feedback voltage divider, and a pass device. The output
current is delivered via the pass device, which is controlled by
the error amplifier, forming a negative feedback system that
ideally drives the feedback voltage to equal the reference voltage.
If the feedback voltage is lower than the reference voltage, the
negative feedback drives more current, increasing the output
voltage. If the feedback voltage is higher than the reference voltage,
the negative feedback drives less current, decreasing the output
voltage. The VBIAS pin is the positive supply for all circuitry
except the pass device.
The ADP130 has an internal soft start that limits the output
voltage ramp period to approximately 200 µs. All internal devices
are controlled by the enable pin, EN. When EN is high, the
output is on; when EN is low, the output is off.
SHUTDOWN
VIN
GND
EN
VOUT
VBIAS
R1
R2
06963-033
SHORT-CIRCUIT,
UVLO, AND
THERMAL
PROTECT
0.5V
REF
Figure 33. Internal Block Diagram
The ADP130 is available in output voltages ranging from 0.8 V to
3.0 V. The ADP130 uses the EN pin to enable and disable the
VOUT pin under normal operating conditions. When EN is
high, VOUT turns on. When EN is low, VOUT turns off. For auto-
matic startup, EN can be tied to VBIAS.
Data Sheet ADP130
Rev. C | Page 13 of 20
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP130 is designed for operation with small, space-saving
ceramic capacitors, but it functions with most commonly used
capacitors as long as care is taken regarding the effective series
resistance (ESR) value. The ESR of the output capacitor affects
the stability of the LDO control loop. A minimum of 0.70 µF
capacitance with an ESR of 1 Ω or less is recommended to ensure
stability of the ADP130. Transient response to changes in load
current is also affected by output capacitance. Using a larger value
of output capacitance improves the transient response of the
ADP130 to large changes in load current. Figure 34 and Figure 35
show the transient responses for output capacitance values of
1 µF and 10 µF, respectively.
06963-034
CH1 200mA CH2 50mV M400ns A CH1 192mA
2
1
T 14%
V
OUT
= 1.8V
C
IN
= C
OUT
= 1µF
1mA TO 350mA LOAD STEP
2.5A/µs
200mA/DIV
I
LOAD
V
OUT
50mV/DIV
Figure 34. Output Transient Response, C
OUT
= 1 μF
06963-035
CH1 200mA CH2 50mV M400ns A CH1 160mA
2
1
T 13%
V
OUT
= 1.8V
C
IN
= C
OUT
= 10µF
1mA TO 350mA LOAD STEP
2.5A/µs
200mA/DIV
I
LOAD
V
OUT
50mV/DIV
Figure 35. Output Transient Response, C
OUT
= 10 μF
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the circuit
sensitivity to PCB layout, especially when long input traces or
high source impedance are encountered. If >1 µF of output
capacitance is required, the input capacitor should be increased
to match it.
Bias Capacitor
Connecting a 1 µF capacitor from VBIAS to GND reduces the
circuit sensitivity to PCB layout, especially when long input traces
or high source impedance are encountered.
Input, Bias, and Output Capacitor Properties
Any good quality ceramic capacitor can be used with the ADP130,
as long as it meets the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics
are not recommended for use with any LDO, due to their poor
temperature and dc bias characteristics.
Figure 36 shows the capacitance vs. voltage bias characteristics
of the 0402 1µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40 to +85°C temperature
range and is not a function of the package or voltage rating.
0
0.2
0.4
0.6
0.8
1.0
1.2
0246810
06963-036
VOLTAGE (V)
CAPACITANCE (µF)
Figure 36. Capacitance vs. Voltage Characteristics
ADP130 Data Sheet
Rev. C | Page 14 of 20
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, compo-
nent tolerance, and voltage.
C
EFF
= C
OUT
× (1 − TEMPCO) × (1 − TOL) (1)
where:
C
EFF
is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, TEMPCO over −40°C to +8C is assumed to be
15% for an X5R dielectric. TOL is assumed to be 10%, and C
OUT
= 0.94 F at 1.8 V, as shown in Figure 36.
Substituting these values in Equation 1 yields the following:
C
EFF
= 0.94 F × (1 − 0.15) × (1 − 0.1) = 0.719 F
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over tempera-
ture and tolerance at the chosen output voltage.
To guarantee the performance of the ADP130, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT
The ADP130 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.1 V. This ensures that the ADP130 inputs
and the output behave in a predictable manner during power-up.
ENABLE FEATURE
The ADP130 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 37,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
06963-037
CH1 500mV CH2 500mV M10ms A CH2 640mV
1
T 30%
2
V
OUT
= 1.8V
C
IN
= C
OUT
= 1µF
V
OUT
500mV/DIV
EN
500mV/DIV
Figure 37. Typical EN Pin Operation
As shown in Figure 37, the EN pin has built-in hysteresis. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
The EN pin active and inactive thresholds are derived from the
V
IN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 38 shows typical EN active and inactive thresholds
when the V
BIAS
voltage varies from 2.3 V to 5.5 V.
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
06963-038
V
BIAS
(V)
THRESHOLD (V)
EN ACTIVE
EN INACTIVE
Figure 38. Typical EN Pin Thresholds vs. Input
The ADP130 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for the 0.8 V option
is approximately 180 µs from the time at which the EN active
threshold is crossed to when the output reaches 90% of its final
value. The start-up time depends somewhat on the output voltage
setting and increases slightly as the output voltage increases.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 100 200 300 400 500 600 700 800 900 1000
06963-039
TIME (µs)
VOLTAGE (V)
V
BIAS
= 2.3V
V
IN
= 3.6V
I
LOAD
= 10mA
ENABLE
3.0V
1.8V
1.2V
0.8V
Figure 39. Typical Start-Up Time for Various Output Voltages

ADP130AUJZ-1.2-R7

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Linear Voltage Regulators 350mA Low Quiescent Crnt CMOS
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