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ADP130AUJZ-1.8-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet ADP130
Rev. C | Page 3 of 20
SPECIFICATIONS
V
IN
= V
OUT
+ 0.4 V, V
BIAS
= 5 V, I
OUT
= 10 mA, C
IN
= 1 F, C
OUT
= 1 F, C
BIAS
= 1 F, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE V
IN
T
J
= −40°C to +125°C 1.2 3.6 V
BIAS VOLTAGE RANGE V
BIAS
T
J
= −40°C to +125°C 2.3 5.5 V
OPERATING SUPPLY CURRENT I
VIN
1
I
OUT
= 0 μA 25 μA
I
OUT
= 0 μA, T
J
= −40°C to +125°C 44 μA
I
OUT
= 1 mA 40 μA
I
OUT
= 1 mA, T
J
= −40°C to +125°C 58 μA
I
OUT
= 100 mA 100 μA
I
OUT
= 100 mA, T
J
= −40°C to +125°C 130 μA
I
OUT
= 350 mA 160 μA
I
OUT
= 350 mA, T
J
= −40°C to +125°C 220 μA
BIAS OPERATING CURRENT I
BIAS
16 μA
T
J
= −40°C to +125°C 28 μA
SHUTDOWN CURRENT I
SD-VIN
EN = GND 0.1 μA
EN = GND, T
J
= −40°C to +85°C 1.0 μA
EN = GND, T
J
= +85°C to +125°C 20 μA
I
SD-VBIAS
EN = GND 0.1 μA
EN = GND, T
J
= −40°C to +125°C 1.0 μA
FIXED OUTPUT VOLTAGE ACCURACY V
OUT
I
OUT
= 10 mA −1 +1 %
1 mA < I
OUT
< 350 mA, V
IN
= (V
OUT
+ 0.4 V) to 3.6 V −2 +2 %
1 mA < I
OUT
< 350 mA, V
IN
= (V
OUT
+ 0.4 V) to 3.6 V,
T
J
= −40°C to +125°C
−3 +3 %
LINE REGULATION ∆V
OUT
/∆V
IN
V
IN
= (V
OUT
+ 0.4 V) to 3.6 V, T
J
= –40°C to +125°C −0.10 +0.10 %/ V
LOAD REGULATION
2
∆V
OUT
/∆I
OUT
I
OUT
= 10 mA to 350 mA 0.001 %/mA
I
OUT
= 10 mA to 350 mA, T
J
= −40°C to +125°C 0.005 %/mA
DROPOUT VOLTAGE
3
V
DROPOUT
I
OUT
= 10 mA, V
BIAS
= 2.3 V, V
OUT
= 3 V 2 mV
I
OUT
= 10 mA, V
BIAS
= 2.3 V, V
OUT
= 3 V,
T
J
= −40°C to +125°C
3.5 mV
I
OUT
= 100 mA, V
BIAS
= 2.3 V, V
OUT
= 3 V 17 mV
I
OUT
= 100 mA, V
BIAS
= 2.3 V, V
OUT
= 3 V,
T
J
= −40°C to +125°C
28 mV
I
OUT
= 350 mA, V
BIAS
= 2.3 V, V
OUT
= 3 V 70 mV
I
OUT
= 350 mA, V
BIAS
= 2.3 V, V
OUT
= 3 V,
T
J
= −40°C to +125°C
100 mV
START-UP TIME
4
T
START-UP
V
OUT
= 1.2 V 200 μs
CURRENT LIMIT THRESHOLD
5
I
LIMIT
400 550 1000 mA
THERMAL SHUTDOWN
Thermal Shutdown Threshold TS
SD
T
J
rising 150
C
Thermal Shutdown Hysteresis TS
SD-HYS
15
C
EN INPUT
EN Input Logic High V
IH
2.3 V ≤ V
BIAS
≤ 5.5 V 1.2 V
EN Input Logic Low V
IL
2.3 V ≤ V
BIAS
≤ 5.5 V 0.4 V
EN Input Leakage Current V
I-LEAKAGE
EN = BIAS or GND 0.1 μA
EN = BIAS or GND, T
J
= −40°C to +125°C 1 μA
UNDERVOLTAGE LOCKOUT UVLO
Input Voltage Rising UVLO
RISE
T
J
= −40°C to +125°C 2.1 V
Input Voltage Falling UVLO
FALL
T
J
= −40°C to +125°C 1.5 V
Hysteresis UVLO
HYS
180 mV
ADP130 Data Sheet
Rev. C | Page 4 of 20
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT NOISE OUT
NOISE
10 Hz to 100 kHz, V
IN
= 3.6 V, V
OUT
= 0.8 V 29 μV rms
10 Hz to 100 kHz, V
IN
= 3.6 V, V
OUT
= 1.2 V 38 μV rms
10 Hz to 100 kHz, V
IN
= 3.6 V, V
OUT
= 1.5 V 43 μV rms
10 Hz to 100 kHz, V
IN
= 3.6 V, V
OUT
= 2.5 V 61 μV rms
10 Hz to 100 kHz, V
IN
= 3.6 V, V
OUT
= 3.0 V 77 μV rms
POWER SUPPLY REJECTION RATIO PSRR
Modulated bias, 10 kHz, V
OUT
= 3.0 V, V
IN
= 3.6 V,
V
BIAS
= 5 V
70 dB
Modulated bias, 100 kHz, V
OUT
= 3.0 V, V
IN
= 3.6 V,
V
BIAS
= 5 V
53 dB
Modulated V
IN
, 10 kHz, V
OUT
= 1.2 V, V
IN
= V
OUT
+ 1 V,
V
BIAS
= 5 V
70 dB
Modulated V
IN
, 100 kHz, V
OUT
= 1.2 V, V
IN
= V
OUT
+ 1 V,
V
BIAS
= 5 V
54 dB
Modulated V
IN
, 10 kHz, V
OUT
= 0.8 V, V
IN
= V
OUT
+ 1 V,
V
BIAS
= 5 V
70 dB
Modulated V
IN
, 100 kHz, V
OUT
= 0.8 V, V
IN
= V
OUT
+ 1 V,
V
BIAS
= 5 V
55 dB
1
I
VIN
= I
GND
− I
BIAS
, where I
GND
is the current flowing from the GND pin.
2
Based on an endpoint calculation using 1 mA and 350 mA loads.
3
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 1.3 V.
4
Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of its nominal value.
5
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 2.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 2.0 V, or 1.8 V.
INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE
1
C
MIN
T
A
= −40°C to +125°C 0.70 1 μF
CAPACITOR ESR R
ESR
T
A
= −40°C to +125°C 0.001 1 Ω
1
The minimum input and output capacitance should be >0.70 μF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and
Z5U capacitors are not recommended for use with any LDO.
Data Sheet ADP130
Rev. C | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND −0.3 V to +3.6 V
VBIAS to GND −0.3 V to +6 V
EN to GND −0.3 V to VBIAS
VOUT to GND −0.3 V to VIN
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Operating Junction Temperature 125°C
Lead Temperature (Soldering, 10 sec) 300°C
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in combi-
nation. The ADP130 may be damaged when junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can exceed
the maximum limit as long as the junction temperature is within
specification limits. The junction temperature (T
J
) of the device
is dependent on the ambient temperature (T
A
), the power
dissipation of the device (P
D
), and the junction-to-ambient thermal
resistance of the package (θ
JA
). T
J
is calculated using the
following formula:
T
J
= T
A
+ (P
D
× θ
JA
)
The junction-to-ambient thermal resistance (θ
JA
) of the package
is based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
JA
may vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θ
JA
are based on a four-layer, 4 in × 3 in circuit board.
For details about board construction, refer to JEDEC JESD51-7.
Ψ
JB
is the junction-to-board thermal characterization parameter
with units of °C/W. Ψ
JB
of the package is based on modeling and
calculation using a four-layer board. The JEDEC JESD51-12
document, Guidelines for Reporting and Using Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. Ψ
JB
measures the component
power flowing through multiple thermal paths rather than a single
path, as in thermal resistance (θ
JB
). Therefore, Ψ
JB
thermal paths
include convection from the top of the package as well as radiation
from the package, factors that make Ψ
JB
more useful in real world
applications. Maximum junction temperature (T
J
) is calculated
from the board temperature (T
B
) and power dissipation (P
D
), using
the following formula:
T
J
= T
B
+ (P
D
× Ψ
JB
)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for
more detailed information about Ψ
JB
.
THERMAL RESISTANCE
θ
JA
and Ψ
JB
are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θ
JA
Ψ
JB
Unit
5-Lead TSOT 170 43 °C/W
ESD CAUTION
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ADP130AUJZ-1.8-R7

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Linear Voltage Regulators 350mA Low Quiescent Crnt CMOS
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