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83054AGILFT

P1-P3P4-P6P7-P9P10-P12P13-P14
83054 Data Sheet
©2015 Integrated Device Technology, Inc December 15, 20154
TABLE 5A. AC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V ± 5%, TA = -40°C TO 85°C
TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage
V
DD
= 3.3V ± 5% 2 V
DD
+ 0.3 V
V
DD
= 2.5V ± 5% 1.7 V
DD
+ 0.3 V
V
IL
Input Low Voltage
V
DD
= 3.3V ± 5% -0.3 0.8 V
V
DD
= 2.5V ± 5% -0.3 0.7 V
I
IH
Input High Current
CLK0:CLK3,
SEL0, SEL1
V
DD
= 3.3V or 2.5V ± 5% 150 µA
OE V
DD
= 3.3V or 2.5V ± 5% 5 µA
I
IL
Input Low Current
CLK0:CLK3,
SEL0, SEL1
V
DD
= 3.3V or 2.5V ± 5% -5 µA
OE V
DD
= 3.3V or 2.5V ± 5% -150 µA
V
OH
Output HighVoltage
V
DDO
= 3.3V ± 5%; NOTE 1 2.6 V
V
DDO
= 2.5V ± 5%; NOTE 1 1.8 V
V
DDO
= 1.8V ± 5%; NOTE 1 V
DD
- 0.3 V
V
OL
Output Low Voltage
V
DDO
= 3.3V ± 5%; NOTE 1 0.5 V
V
DDO
= 2.5V ± 5%; NOTE 1 0.45 V
V
DDO
= 1.8V ± 5%; NOTE 1 0.35 V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement section, “Load Test Circuit” diagrams.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 2.4 2.7 3.0 ns
tp
HL
Propagation Delay, High to Low; NOTE 1 2.5 2.7 2.9 ns
tsk(i) Input Skew; NOTE 2 55 225 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 3
155.52MHz,
(12kHz to 20MHz)
0.19 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 50 500 ps
odc Output Duty Cycle 45 55 %
MUX
ISOL
MUX Isolation @ 100MHz 45 dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
83054 Data Sheet
©2015 Integrated Device Technology, Inc December 15, 20155
TABLE 5B. AC CHARACTERISTICS, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, TA = -40°C TO 85°C
TABLE 5C. AC CHARACTERISTICS, V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 2.5 2.8 3.1 ns
tp
HL
Propagation Delay, High to Low; NOTE 1 2.6 2.8 3.0 ns
tsk(i) Input Skew; NOTE 2 45 150 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 3
155.52MHz,
(12kHz to 20MHz)
0.14 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 50 500 ps
odc Output Duty Cycle 45 55 %
MUX
ISOL
MUX Isolation @ 100MHz 45 dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 2.7 3.2 3.8 ns
tp
HL
Propagation Delay, High to Low; NOTE 1 2.8 3.3 3.8 ns
tsk(i) Input Skew; NOTE 2 50 150 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 3
155.52MHz,
(12kHz to 20MHz)
0.16 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 100 700 ps
odc Output Duty Cycle 45 55 %
MUX
ISOL
MUX Isolation @ 100MHz 45 dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
83054 Data Sheet
©2015 Integrated Device Technology, Inc December 15, 20156
TABLE 5D. AC CHARACTERISTICS, V
DD
= V
DDO
= 2.5V ± 5%, TA = -40°C TO 85°C
TABLE 5E. AC CHARACTERISTICS, V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ± -5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 2.5 3.0 3.5 ns
tp
HL
Propagation Delay, High to Low; NOTE 1 2.5 2.9 3.4 ns
tsk(i) Input Skew; NOTE 2 60 175 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 3
155.52MHz,
(12kHz to 20MHz)
0.21 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 100 500 ps
odc Output Duty Cycle 40 60 %
MUX
ISOL
MUX Isolation @ 100MHz 45 dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High; NOTE 1 2.6 3.3 4.0 ns
tp
HL
Propagation Delay, High to Low; NOTE 1 2.7 3.3 4.0 ns
tsk(i) Input Skew; NOTE 2 50 150 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 3
155.52MHz,
(12kHz to 20MHz)
0.17 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 100 700 ps
odc Output Duty Cycle 40 60 %
MUX
ISOL
MUX Isolation @ 100MHz 45 dB
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
P1-P3P4-P6P7-P9P10-P12P13-P14

83054AGILFT

Mfr. #:
Buy 83054AGILFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 4:1 Single Ended MUX
Lifecycle:
New from this manufacturer.
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