TC74VHCT573AF/AFT/AFK
2014-03-01
5
AC Characteristics
(input: t
r
= t
f
= 3 ns)
Test Condition Ta = 25°C
Ta =
−40 to 85°C
Characteristics Symbol
V
CC
(V) C
L
(pF) Min Typ. Max Min Max
Unit
15 ― 7.7 12.3 1.0 13.5
Propagation delay
time
(LE-Q)
t
pLH
t
pHL
― 5.0 ± 0.5
50 ― 8.5 13.3 1.0 14.5
ns
15 ― 5.1 8.5 1.0 9.5
Propagation delay
time
(D-Q)
t
pLH
t
pHL
― 5.0 ± 0.5
50 ― 5.9 9.5 1.0 10.5
ns
15 ― 6.3 10.9 1.0 12.5
3-state output enable
time
t
pZL
t
pZH
R
L
= 1 kΩ 5.0 ± 0.5
50 ― 7.1 11.9 1.0 13.5
ns
3-state output disable
time
t
pLZ
t
pHZ
R
L
= 1 kΩ 5.0 ± 0.5 50 ― 8.8 11.2 1.0 12.0 ns
Output to output skew
t
osLH
t
osHL
(Note 1) 5.0 ± 0.5 50 ― ― 1.0 ― 1.0 ns
Input capacitance C
IN
― ― 4 10 ― 10 pF
Output capacitance C
OUT
― ― 9 ― ― ― pF
Power dissipation
capacitance
C
PD
(Note 2) ― 25 ― ― ― pF
Note 1: Parameter guaranteed by design.
t
osLH
= |t
pLHm
− t
pLHn
|, t
osHL
= |t
pHLm
− t
pHLn
|
Note 2: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr)
= C
PD
·V
CC
·f
IN
+ I
CC
/ 8 (per latch)
And the total C
PD
when n pcs. of latch operate can be gained by the following equation:
C
PD
(total) = 14 + 11·n
Noise Characteristics
(input: t
r
= t
f
= 3 ns)
Test Condition Ta = 25°C
Characteristics Symbol
V
CC
(V) Typ. Limit
Unit
Quiet output maximum dynamic V
OL
V
OLP
C
L
= 50 pF 5.0 1.1 1.5 V
Quiet output minimum dynamic V
OL
V
OLV
C
L
= 50 pF 5.0 −1.1 −1.5 V
Minimum high level dynamic input voltage V
IHD
C
L
= 50 pF 5.0 ― 2.0 V
Maximum low level dynamic input voltage V
ILD
C
L
= 50 pF 5.0 ― 0.8 V
