74ACTQ16374MTD

© 2005 Fairchild Semiconductor Corporation DS010935 www.fairchildsemi.com
June 1991
Revised May 2005
74ACTQ16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
74ACTQ16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ16374 contains sixteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte
and can be shorted together for full 16-bit operation.
The ACTQ16245 utilizes Fairchild Quiet Series
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series
fea-
tures GTO
output control for superior performance.
Features
Utilizes Fairchild FACT Quiet Series technology
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin output skew
Buffered Positive edge-triggered clock
Separate control logic for each byte
16-bit version of the ACTQ374
Outputs source/sink 24 mA
Additional specs for Multiple Output Switching
Output loadings specs for both 50 pF and 250 pF loads
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
FACT , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ16374SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ACTQ16374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin
Description
Names
OE
n
Output Enable Input (Active LOW)
CP
n
Clock Pulse Input
I
0
I
15
Inputs
O
0
O
15
Outputs
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74ACTQ16374
Functional Description
The ACTQ16374 consists of sixteen edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The device is byte controlled with each byte function-
ing identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP
n
)
transition. With the Output Enable (OE
n
) LOW, the con-
tents of the flip-flops are available at the outputs. When
OE
n
is HIGH, the outputs go to the high impedance state.
Operation of the OE
n
input does not affect the state of the
flip-flops.
Truth Tables
H HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
HIGH Impedance
LOW-to-HIGH Transition
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Inputs Outputs
CP
1
OE
1
I
0
–I
7
O
0
–O
7
LH H
LL L
L L X (Previous)
XHX Z
Inputs Outputs
CP
2
OE
2
I
8
–I
15
O
8
–O
15
LH H
LL L
L L X (Previous)
XHX Z
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74ACTQ16374
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n
1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n
1) outputs are switched HIGH and one output held HIGH.
Note 7: Maximum number of data inputs (n) switching. (n
1) input switching 0V to 3V (ACTQ). Input under test switching 3V to threshold (V
ILD
).
Supply Voltage (V
CC
) 0.5V to 7.0V
DC Input Diode Current (I
IK
)
V
I
0.5V 20 mA
V
I
V
CC
0.5V 20 mA
DC Output Diode Current (I
OK
)
V
O
0.5V 20 mA
V
O
V
CC
0.5V 20 mA
DC Output Voltage (V
O
) 0.5V to V
CC
0.5V
DC Output Source/Sink Current (I
O
) 50 mA
DC V
CC
or Ground Current
per Output Pin
50 mA
Storage Temperature
65 C to 150 C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (V
O
)0V to V
CC
Operating Temperature (T
A
) 40 C to 85 C
Minimum Input Edge Rate (
V/ t) 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol Parameter
V
CC
T
A
25 CT
A
40 C to 85 C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH 4.5 1.5 2.0 2.0
V
V
OUT
0.1V
Input Voltage 5.5 1.5 2.0 2.0 or V
CC
0.1V
V
IL
Maximum LOW 4.5 1.5 0.8 0.8
V
V
OUT
0.1V
Input Voltage 5.5 1.5 0.8 0.8 or V
CC
0.1V
V
OH
Minimum HIGH 4.5 4.49 4.4 4.4
V
I
OUT
50 A
Output Voltage 5.5 5.49 5.4 5.4
V
IN
V
IL
or V
IH
4.5 3.86 3.76 V I
OH
24 mA
5.5 4.86 4.76 I
OH
24 mA (Note 2)
V
OL
Maximum LOW 4.5 0.001 0.1 0.1
V
I
OUT
50 A
Output Voltage 5.5 0.001 0.1 0.1
V
IN
V
IL
or V
IH
4.5 0.36 0.44 V I
OL
24 mA
5.5 0.36 0.44 I
OL
24 mA (Note 2)
I
OZ
Maximum 3-STATE 5.5 0.5 5.0 AV
I
V
IL
, V
IH
Leakage Current V
O
V
CC
, GND
I
IN
Maximum Input Leakage Current 5.5 0.1 1.0 AV
I
V
CC
, GND
I
CCT
Maximum I
CC
/Input 5.5 0.6 1.5 mA V
I
V
CC
2.1V
I
CC
Maximum Quiescent Supply Current 5.5 8.0 80.0 AV
IN
V
CC
or GND
I
OLD
Minimum Dynamic
5.5
75 mA V
OLD
1.65V Max
I
OHD
Output Current (Note 3) 75 mA V
OHD
3.85V Min
V
OLP
Quiet Output Maximum 5.0 0.5 0.8 V Figure 1, Figure 2
Dynamic V
OL
(Note 5)(Note 6)
V
OLV
Quiet Output
5.0 0.5 1.0 V
Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 5)(Note 6)
V
OHP
Maximum Overshoot 5.0 V
OH
1.0 V
OH
1.5 V Figure 1, Figure 2
(Note 4)(Note 6)
V
OHV
Minimum V
CC
Droop 5.0 V
OH
1.0 V
OH
1.8 V Figure 1, Figure 2
(Note 4)(Note 6)
V
IHD
Minimum HIGH Dynamic Input Voltage Level 5.0 1.7 2.0 V (Note 4)(Note 7)
V
ILD
Maximum LOW Dynamic Input Voltage Level 5.0 1.2 0.8 V (Note 4)(Note 7)

74ACTQ16374MTD

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Flip Flops 16-Bit D Flip-Flop
Lifecycle:
New from this manufacturer.
Delivery:
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