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74ALVCH16841DGGY

P1-P3P4-P6P7-P9P10-P11
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
1998 Jul 27
6
AC CHARACTERISTICS FOR V
CC
= 2.3V TO 2.7V RANGE
GND = 0V; t
r
= t
f
≤ 2.0ns; C
L
= 30pF
LIMITS
SYMBOL PARAMETER WAVEFORM V
CC
= 2.3 to 2.7V UNIT
MIN TYP
1
MAX
t
PLH
/t
PHL
Propagation delay
nD
n
to nQ
n
1, 5 1.0 2.5 5.0 ns
t
PLH
/t
PHL
Propagation delay
nLE to nQ
n
2, 5 1.0 2.5 5.6 ns
t
PZH
/t
PZL
3-State output enable time
nOE
n
to nQ
n
4, 5 1.0 2.7 6.2 ns
t
PHZ
/t
PLZ
3-State output disable time
nOE
n
to nQ
n
4, 5 1.1 2.2 5.3 ns
t
W
nLE pulse width HIGH 2, 5 3.3 1.5 – ns
t
SU
Set up time nD
n
to nLE 3, 5 1.3 0.1 – ns
T
h
Hold time nD
n
to nLE 3, 5 1.4 0.3 – ns
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
AC CHARACTERISTICS FOR V
CC
= 3.0V TO 3.6V RANGE AND V
CC
= 2.7V
GND = 0V; t
r
= t
f
≤ 2.5ns; C
L
= 50pF
LIMITS LIMITS
SYMBOL PARAMETER WAVEFORM V
CC
= 3.3 ± 0.3V V
CC
= 2.7V UNIT
MIN TYP
1,
2
MAX MIN TYP
1
MAX
t
PLH
/t
PHL
Propagation delay
nD
n
to nQ
n
1, 5 1.0 2.4 3.9 1.0 2.6 4.7 ns
t
PLH
/t
PHL
Propagation delay
nLE to nQ
n
2, 5 1.0 2.4 4.3 1.0 2.6 5.1 ns
t
PZH
/t
PZL
3-State output enable time
nOE
n
to nQ
n
4, 5 1.0 2.3 4.9 1.0 3.1 6.0 ns
t
PHZ
/t
PLZ
3-State output disable time
nOE
n
to nQ
n
4, 5 1.3 2.9 4.1 1.3 3.1 4.3 ns
t
W
nLE pulse width HIGH 2, 5 3.3 1.5 – 3.3 1.5 – ns
t
SU
Set up time nD
n
to nLE 3, 5 1.0 0.6 – 1.1 0.1 – ns
t
h
Hold time nD
n
to nLE 3, 5 1.4 0.2 – 1.7 0.2 – ns
NOTES:
1. All typical values are measured T
amb
= 25°C.
2. Typical value is measured at V
CC
= 3.3V
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
1998 Jul 27
7
AC WAVEFORMS FOR V
CC
= 2.3V TO 2.7V AND
V
CC
< 2.3V RANGE
V
M
= 0.5 V
CC
V
X
= V
OL
+ 0.15V
V
Y
= V
OH
–0.15V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
AC WAVEFORMS FOR V
CC
= 3.0V TO 3.6V AND
V
CC
= 2.7V RANGE
V
M
= 1.5 V
V
X
= V
OL
+ 0.3V
V
Y
= V
OH
–0.3V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= 2.7V
V
I
= V
CC
D
n
INPUT
t
PHL
t
PLH
V
OL
V
I
GND
V
OH
Q
n
OUTPUT
V
M
V
M
SH00153
Waveform 1. The input (D
n
) to output (Q
n
) propagation delay
LE INPUT
Qn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
V
M
V
M
V
M
SH00150
Waveform 2. The latch enable (LE) pulse width, the latch enable
input to output (Q
n
) propagation delay
Dn
INPUT
LE
INPUT
t
SU
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
t
SU
th
V
I
GND
V
I
GND
V
M
V
M
SH00149
Waveform 3. The data set up and hold times for the D
n
input to
the LE input
t
PLZ
t
PZL
V
I
nOE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SH00137
Waveform 4. 3-State enable and disable times
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
V
CC
R
L
= 500 Ω
Test Circuit for switching times
Open
GND
S
1
DEFINITIONS
V
CC
V
I
< 2.7V V
CC
TEST S
1
t
PLH/
t
PHL
Open
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
2 V
CC
t
PLZ/
t
PZL
2.7V2.7–3.6V
t
PHZ/
t
PZH
GND
R
L
= 500 Ω
2 * V
CC
SV00906
Waveform 5. Load circuitry for switching times
Philips Semiconductors Product specification
74ALVCH16841
20-bit bus interface D-type latch (3-State)
1998 Jul 27
8
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1
P1-P3P4-P6P7-P9P10-P11

74ALVCH16841DGGY

Mfr. #:
Buy 74ALVCH16841DGGY
Manufacturer:
Nexperia
Description:
Latches 20-Bit Bus Interface D-Type, Latch
Lifecycle:
New from this manufacturer.
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