WM7230 Pre-Production
w
PP, Rev 3.1, January 2014
6
TERMINOLOGY
1. Sensitivity (dBFS) – Sensitivity is a measure of the microphone output response to the acoustic pressure of a 1kHz
94dB SPL (1Pa RMS) sine wave. This is referenced to the output Full Scale Range (FSR) of the microphone.
2. Full Scale Range (FSR) - Sensitivity, Electrical Noise Floor and Power Supply Rejection are measured with reference
to the output Full Scale Range (FSR) of the microphone. FSR is defined as the amplitude of a 1kHz sine wave output
whose positive peak value reaches 100% density of logic 1s and whose negative peak value reaches 0% density of
logic 1s. This is the largest undistorted 1kHz sine wave that will fit in the digital output numerical range. Note that,
because the definition of FSR is based on a sine wave, it is possible to support a square wave test signal output
whose level is +3dBFS.
3. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the output response of a 1kHz 94dB
SPL sine wave and the idle noise output.
4. Total Harmonic Distortion (%) – THD is the ratio of the RMS sum of the harmonic distortion products in the specified
bandwidth (see note below) relative to the RMS amplitude of the fundamental (ie. test frequency) output.
5. All performance measurements are carried out with 20kHz low pass ‘brick-wall’ filter and, where noted, an A-weighted
filter. Failure to use these filters will result in higher THD and lower SNR values than are found in the Acoustic and
Electrical Characteristics. The brick wall filter removes out of band noise.
6. SLEEP Mode is enabled when the CLK input is below the CLK Sleep Frequency noted above. This is a power-saving
mode. Normal operation resumes automatically when the CLK input is above the CLK Sleep Frequency. Note that the
VDD supply is still required in SLEEP mode.
AUDIO INTERFACE TIMING
t
L_EN
CLK
(input)
t
L_DIS
t
R_EN
t
R_DIS
t
CY
DAT is high-impedance (hi-z) when not outputting data
DAT
(LRSEL = 1)
DAT
(LRSEL = 0)
Figure 1 Digital Microphone Interface Timing
Test Conditions
The following timing information is valid across the full range of recommended operating conditions.
PARAMETER SYMBOL MIN TYP MAX UNIT
Digital Microphone Interface Timing
CLK cycle time t
CY
308 1000 ns
CLK duty cycle 60:40 40:60
DAT enable from rising CLK edge (LRSEL = 1) t
L_EN
18 ns
DAT disable from falling CLK edge (LRSEL = 1) t
L_DIS
16 ns
DAT enable from falling CLK edge (LRSEL = 0) t
R_EN
18 ns
DAT disable from rising CLK edge (LRSEL = 0) t
R_DIS
16 ns
