ISL97632IRT18Z-T

7
FN9239.3
March 22, 2010
Applications
Efficiency Improvement
Figure 2 on page 5 shows the efficiency measurements. The
choice of the inductor has a significant impact on the power
efficiency. As shown in Equation 4, the higher the
inductance, the lower the peak current therefore the lower
the conduction and switching losses. On the other hand, it
has also a higher series resistance. Nevertheless, the
efficiency improvement from lowering the peak current is
greater than the impact of the resistance increase with larger
value of inductor. Efficiency can also be improved for
systems that have high supply voltages. Since the ISL97632
can only supply from 2.4V to 5.5V, V
IN
must be separated
from the high supply voltage for the boost circuit as shown in
Figure 7 and the efficiency improvement is shown in
Figure 8.
9 LEDs Operation
For medium size LCDs that need more than 7 low power
LEDs for backlighting, such as a Portable Media Player or
Automotive Navigation Panel displays, the voltage range of
the ISL97632 is not sufficient. However, the ISL97632 can
be used as an LED controller with an external protection
MOSFET connected in cascode fashion to achieve higher
output voltage. A conceptual 9 LEDs driver circuit is shown
in Figure 9. A 40V logic level N-Channel MOSFET is
configured such that its drain ties between the inductor and
the anode of Schottky diode, its gate ties to the input, and its
source ties to the ISL97632 LX node connecting to the drain
of the internal switch. When the internal switch turns on, it
pulls the source of M1 down to ground, and LX conducts as
normal. When the internal switch turns off, the source of M1
will be pulled up by the follower action of M1, limiting the
maximum voltage on the ISL97632 LX pin to below V
IN
, but
allowing the output voltage to go much higher than the
breakdown limit on the LX pin. The switch current limit and
maximum duty cycle will not be changed by this setup, so
input voltage will need to be carefully considered to make
sure that the required output voltage and current levels are
achievable. Because the source of M1 is effectively floating
when the internal LX switch is off, the drain-to-source
capacitance of M1 may be sufficient to capacitively pull the
node high enough to breaks down the gate oxide of M1. To
prevent this, V
OUT
should be connected to V
IN
, allowing the
internal Schottky to limit the peak voltage. This will also hold
the V
OUT
pin at a known low voltage, preventing the built in
OVP function from causing problems. This OVP function is
effectively useless in this mode as the real output voltage is
outside its intended range. If the user wants to implement
their own OVP protection (to prevent damage to the output
capacitor, they should insert a zener from V
OUT
to the FB
pin. In this setup, it would be wise not to use the FBSW to FB
switch as otherwise the zener will have to be a high power
one capable of dissipating the entire LED load power. Then
the LED stack can then be connected directly to the sense
resistor and via a 10k resistor to FB. A zener can be placed
from V
OUT
to the FB pin allowing an over voltage event to
pull up on FB with a low breakdown current (and thus low
power zener) as a result of the 10k resistor.
Vs = 12V
L1
22µH
1 2
R1
4
C3
0.22µF
D2
D3
D1
D5
D6
D4
ISL97632
FBSW
LX
VOUT
SDIN
VIN
FB
GND
C1
1µF
25mA
C2
0.1µF
EN
V
IN
= 2.7V TO 5.5V
FIGURE 7. SEPARATE HIGH INPUT VOLTAGE FOR HIGHER
EFFICIENCY OPERATION
5 101520
90
85
70
0
75
80
25 30
ILED (mA)
EFFICIENCY (%)
V
IN
= 4V
6 LEDs
L1 = 22µH
R1 = 4
V
S
= 12V
V
S
= 9V
FIGURE 8. EFFICIENCY IMPROVEMENT WITH 9V AND 12V
INPUTS
ISL97632
8
FN9239.3
March 22, 2010
SEPIC Operation
For applications where the output voltage is not always
above the input voltage, a buck or boost regulation is
needed. A SEPIC (Single Ended Primary Inductance
Converter) topology, (see Figure 10), can be considered for
such an application. A single cell Li-Ion battery operating a
cellphone backlight or flashlight is one example. The
battery voltage is between 2.5V and 4.2V depending on the
state of charge. On the other hand, the output may require
only one 3V to 4V medium power LED for illumination
because the light guard of the backlight assembly is
optimized or it is a cost efficiency trade off reason.
In fact, a SEPIC configured LED driver is flexible enough to
allow the output to be well above or below the input voltage,
unlike the previous example. Another example is when the
number of LEDs and input requirements are different from
platform to platform, a common circuit and PCB that fit all the
platforms, in some cases, may be beneficial enough that
it
outweighs the disadvantage of adding additional component
cost. L1 and L2 can be a coupled inductor in one package.
The simplest way to understand SEPIC topology is to think
about it as a boost regulator in which the input volute is level
shifted downward at the same magnitude and the lowest
reference level starts at -V
IN
rather than 0V.
The SEPIC works as follows: Assume the circuit in Figure 10
operates normally when the ISL97632 internal switch opens,
and it is in the PWM ‘OFF’ state. After a short duration where
few LC time constants elapsed, the circuit is considered in
the steady-state within the PWM ‘OFF’ period that L1 and L2
are shorted. V
B
is therefore shorted to the ground and C3 is
charged to V
IN
with V
A
= V
IN
. When the ISL97632 internal
switch closes, and the circuit is in the PWM on state, V
A
is
now pulled to ground. Since the voltage in C3 cannot be
changed instantaneously, V
B
is shifted downward and
becomes -V
IN
. The next cycle, when the ISL97632 switch
opens, V
B
boosts up to the targeted output like the standard
boost regulator operation, except the lowest reference point
is at -V
IN
. The output is approximated as shown in
Equation 5:
where D is the on-time of the PWM duty cycle.
The convenience of SEPIC comes with some trade off in
addition to the additional L and C costs. The efficiency is
usually lowered because of the relatively large efficiency
loss through the Schottky diode if the output voltage is low.
The L2 series resistance also contributes additional loss.
Figure 11 shows the efficiency measurement of a single LED
application as the input varies between 2.7V and 4.2V.
Note, V
B
is considered the level-shifted LX node of a
standard boost regulator. The higher the input voltage, the
lower the V
B
voltage will be during PWM on period. The
result is that the efficiency will be lower at higher input
voltages because the SEPIC has to work harder to boost up
to the required level. This behavior is the opposite to the
standard boost regulator’s and the comparison is shown in
Figure 11.
PCB Layout Considerations
The layout is very important for the converter to function
properly. R
SET
must be located as close as possible to the FB
and GND pins. Longer traces to the LEDs are acceptable.
Similarly, the supply decoupling capacitor and the output filter
capacitor should be as close as possible to the VIN and
VOUTpins.
The heat of the IC is mainly dissipated through the thermal
pad of the package. Maximize the copper area connected to
this pad if possible. In addition, a solid ground plane is always
helpful for the EMI performance.
C1
1µF
L1
22µH
1
2
V
A
V
B
VIN = 2.7V to 5.5V
22µH
L2
C3
1µF
C4
0.22µ
D1
R1
1
C2
0.1µF
VIN
EN
SDIN
LX
VOUT
FBSW
FB
GND
FIGURE 10. SEPIC LED DRIVER
V
OUT
V
IN
D
1D
------------------
=
(EQ. 5)
V
IN
= 2.7V
V
IN
= 4.2V
1 LED
L1 = L2 = 22µH
C3 = 1µF
R1 = 4.7
0 5 10 15 20
ILED (mA)
EFFICIENCY (%)
76
72
68
64
60
FIGURE 11. EFFICIENCY MEASUREMENT OF 1 LED SEPIC
DRIVER
ISL97632
9
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9239.3
March 22, 2010
ISL97632
Thin Dual Flat No-Lead Plastic Package (TDFN)
//
NX (b)
SECTION "C-C"
5
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C
C
0.10
0.08
SIDE VIEW
0.15
2X
E
A
B
C0.15
D
TOP VIEW
CB
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
N
(Nd-1)Xe
(DATUM A)
(DATUM B)
5
0.10
87
D2
BA
M
C
N-1
12
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
FOR EVEN TERMINAL/SIDE
TERMINAL TIP
C
L
e
L
CC
L8.2x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.70 0.75 0.80 -
A1 - - 0.05 -
A3 0.20 REF -
b 0.20 0.25 0.32 5,8
D 2.00 BSC -
D2 1.50 1.65 1.75 7,8
E 3.00 BSC -
E2 1.65 1.80 1.90 7,8
e 0.50 BSC -
k0.20 - - -
L 0.30 0.40 0.50 8
N82
Nd 4 3
Rev. 0 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

ISL97632IRT18Z-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LED Display Drivers 3/4/6 LED DRVR W/ DIGTL DIM 18V
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union