© 2002 Fairchild Semiconductor Corporation DS009588 www.fairchildsemi.com
April 1988
Revised January 2002
74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register
74F676
16-Bit Serial/Parallel-In, Serial-Out Shift Register
General Description
The 74F676 contains 16 flip-flops with provision for syn-
chronous parallel or serial entry and serial output. When
the Mode (M) input is HIGH, information present on the
parallel data (P
0
–P
15
) inputs is entered on the falling edge
of the Clock Pulse (CP
) input signal. When M is LOW, data
is shifted out of the most significant bit position while infor-
mation present on the Serial (SI) input shifts into the least
significant bit position. A HIGH signal on the Chip Select
(CS
) input prevents both parallel and serial operations.
Features
■ 16-bit parallel-to-serial conversion
■ 16-bit serial-in, serial-out
■ Chip select control
■ Slim 24 lead 300 mil package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F676SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74F676PC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide
74F676SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
