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NCP3065D3SLDGEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
NCP3065, NCV3065
http://onsemi.com
7
INTRODUCTION
The NCP3065 is a monolithic power switching regulator
optimized for LED Driver applications. Its flexible
architecture enables the system designer to directly
implement a step−up or step−down topology with a
minimum number of external components for driving LEDs.
A representative block diagram is shown in Figure 4.
OPERATING DESCRIPTION
The NCP3065 operates as a fixed oscillator frequency
output voltage ripple gated regulator. In general, this mode
of operation is somewhat analogous to a capacitor charge
pump and does not require dominant pole loop
compensation for converter stability. The typical operating
waveforms are shown in Figure 14. The output voltage
waveform shown is for a step−down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that the
output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty cycle
controlled by the oscillator, thus pumping up the output filter
capacitor. When the feedback voltage level reaches nominal
comparator value, the output switch cycle is inhibited. When
the load current causes the output voltage to fall below the
nominal value feedback comparator enables switching
immediately. Under these conditions, the output switch
conduction can be enabled for a partial oscillator cycle, a
partial cycle plus a complete cycle, multiple cycles, or a
partial cycle plus multiple cycles.
Oscillator
The oscillator frequency and off−time of the output switch
are programmed by the value of the timing capacitor C
T
.
Capacitor C
T
is charged and discharged by a 1 to 6 ratio
internal current source and sink, generating a positive going
sawtooth waveform at Pin 3. This ratio sets the maximum
t
ON
/(t
ON
+t
OFF
) of the switching converter as 6/(6+1) or
85.7% (typical). The oscillator peak and valley voltage
difference is 500 mV typically. To calculate the C
T
capacitor
value for required oscillator frequency, use the equations
found in Figure 22. An online NCP3065 design tool can be
found at www.onsemi.com, which adds in selecting
component values.
Figure 14. Typical Operating Waveforms
1
0
Output Switch
1
0
On
Off
Feedback Comparator Output
Nominal Output Voltage Level
Startup Operation
Output Voltage
Timing Capacitor, C
T
I
PK
Comparator Output
NCP3065, NCV3065
http://onsemi.com
8
Peak Current Sense Comparator
Under normal conditions, the output switch conduction is
initiated by the Voltage Feedback comparator and
terminated by the oscillator. Abnormal operating conditions
occur when the converter output is overloaded or when
feedback voltage sensing is lost. Under these conditions, the
I
pk
Current Sense comparator will protect the Darlington
output Switch. The switch current is converted to a voltage
by inserting a fractional ohm resistor, R
SC
, in series with
V
CC
and the Darlington output switch. The voltage drop
across R
SC
is monitored by the Current Sense comparator.
If the voltage drop exceeds 200 mV (nom) with respect to
V
CC
, the comparator will set the latch and terminate the
output switch conduction on a cycle−by−cycle basis. This
Comparator/Latch configuration ensures that the Output
Switch has only a single on−time during a given oscillator
cycle.
Real
V
turn−off
on
R
s
Resistor
t_delay
I1
Io
di/dt slope
I through the
Darlington
Switch
V
ipk(sense)
The V
IPK(Sense)
Current Limit Sense Voltage threshold is
specified at static conditions. In dynamic operation the
sensed current turn−off value depends on comparator
response time and di/dt current slope.
Real V
turn−off
on R
sc
resistor
V
turn_off
+ V
ipk(sense)
) Rsc @ (t_delay @ dińdt)
Typical I
pk
comparator response time t_delay is 350 ns.
The di/dt current slope is dependent on the voltage
difference across the inductor and the value of the inductor.
Increasing the value of the inductor will reduce the di/dt
slope.
It is recommended to verify the actual peak current in the
application at worst conditions to be sure that the max peak
current will never get over the 1.5 A Darlington Switch
Current max rating.
Thermal Shutdown
Internal thermal shutdown circuitry is provided to protect
the IC in the event that the maximum junction temperature
is exceeded. When activated, typically at 165°C, the
Darlington Output Switch is disabled. The temperature
sensing circuit is designed with some hysteresis. The
Darlington Switch is enabled again when the chip
temperature decreases under the low threshold. This feature
is provided to prevent catastrophic failures from accidental
device overheating. It is not intended to be used as a
replacement for proper heatsinking.
LED Dimming
The COMP pin of the NCP3065 is used to provide
dimming capability. In digital input mode the PWM input
signal inhibits switching of the regulator and reduces the
average current through the LEDs. In analog input mode a
PWM input signal is RC filtered and the resulting voltage is
summed with the feedback voltage thus reduces the average
current through the LEDs. Figure 15 illustrated the linearity
of the digital dimming function with a 200 Hz digital PWM.
For further information on dimming control refer to
application note AND8298.
12 V
in
, V
f
= 3.6 V
24 V
in
, V
f
= 3.6 V
24 V
in
, V
f
= 7.2 V
Figure 15.
DUTY CYCLE (%)
1007060504020100
0
100
200
300
500
600
700
I
LED
(mA)
400
800
30 9080
No Output Capacitor Operation
A constant current buck regulator such as the NCP3065
focuses on the control of the current through the load, not the
voltage across it. The switching frequency of the NCP3065
is in the range of 100−250 kHz which is much higher than
the human eye can detect. This allows us to relax the ripple
current specification to allow higher peak to peak values.
This is achieved by configuring the NCP3065 in a
continuous conduction buck configuration with low peak to
peak ripple thus eliminating the need for an output filter
capacitor. The important design parameter is to keep the
peak current below the maximum current rating of the LED.
Using 15% peak to peak ripple results in a good compromise
between achieving max average output current without
exceeding the maximum limit. This saves space and reduces
part count for applications that require a compact footprint.
(Example: See Figure 17) See application note AND8298
for more information.
Output Switch
The output switch is designed in a Darlington
configuration. This allows the application designer to
operate at all conditions at high switching speed and low
voltage drop. The Darlington Output Switch is designed to
switch a maximum of 40 V collector to emitter voltage and
current up to 1.5 A.
NCP3065, NCV3065
http://onsemi.com
9
APPLICATIONS
Figures 16 through 24 show the simplicity and flexibility
of the NCP3065. Two main converter topologies are
demonstrated with actual test data shown below each of the
circuit diagrams.
Figure 16 gives the relevant design equations for the key
parameters. Additionally, a complete application design aid
for the NCP3065 can be found at www.onsemi.com.
(See Notes 8, 9, 10) Step−Down Step−Up
t
on
t
off
V
out
) V
F
V
in
* V
SWCE
* V
out
V
out
) V
F
* V
in
V
in
* V
SWCE
t
on
t
on
t
off
f
ǒ
t
on
t
off
) 1
Ǔ
t
on
t
off
f
ǒ
t
on
t
off
) 1
Ǔ
C
T
C
T
+
381.6 @ 10
*6
f
osc
* 343 @ 10
*12
I
L(avg)
I
out
I
out
ǒ
t
on
t
off
) 1
Ǔ
I
pk
(Switch)
I
L(avg)
)
DI
L
2
I
L(avg)
)
DI
L
2
R
SC
0.20
I
pk (Switch)
0.20
I
pk (Switch)
L
ǒ
V
in
* V
SWCE
* V
out
DI
L
Ǔ
t
on
ǒ
V
in
* V
SWCE
DI
L
Ǔ
t
on
V
ripple(pp)
DI
L
ǒ
1
8 f C
O
Ǔ
2
) (ESR)
2
Ǹ
[
t
on
I
out
C
O
) DI
L
@ ESR
V
out
V
TH
ǒ
R
2
R
1
) 1
Ǔ
V
TH
ǒ
R
2
R
1
) 1
Ǔ
I
out
V
ref
ńR
sense
V
ref
ńR
sense
8. V
SWCE
− Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 7, 8, 9 and 10.
9. V
F
− Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V.
10.The calculated t
on
/t
off
must not exceed the minimum guaranteed oscillator charge to discharge ratio.
Figure 16. Design Equations
The Following Converter Characteristics Must Be Chosen:
V
in
− Nominal operating input voltage.
V
out
− Desired output voltage.
I
out
− Desired output current.
DI
L
− Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DI
L
be chosen to be
less than 10% of the average inductor current I
L(avg)
. This will help prevent I
pk
(Switch)
from reaching the current limit threshold
set by R
SC
. If the design goal is to use a minimum inductance value, let DI
L
= 2(I
L(avg)
). This will proportionally reduce
converter output current capability.
f − Maximum output switch frequency.
V
ripple(pp)
− Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low
value since it will directly affect line and load regulation. Capacitor C
O
should be a low equivalent series resistance (ESR)
electrolytic designed for switching regulator applications.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

NCP3065D3SLDGEVB

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