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NLSF3T126MNR2

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 5
1 Publication Order Number:
NLSF3T126/D
NLSF3T126
Quad Bus Buffer
with 3−State Control Inputs
The NLSF3T126 is a high speed CMOS quad bus buffer fabricated
with silicon gate CMOS technology. It achieves noninverting high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The NLSF3T126 requires the 3−state control input (OE) to be set
Low to place the output into high impedance.
The T126 inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V, because it has
full 5.0 V CMOS level output swings.
The NLSF3T126 input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V
CC
= 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
• High Speed: t
PD
= 3.8 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 4.0 mA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V,
Machine Model > 200 V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• Pb−Free Package is Available*
L
H
X
H
H
L
FUNCTION TABLE
Inputs Output
AOE
L
H
Z
Y
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING DIAGRAM
Device Package Shipping
†
ORDERING INFORMATION
NLSF3T126MNR2 QFN−16 3000/Tape & Ree
l
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
NLSFT126 = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
16
NLSF
T126
ALYW G
G
1
NLSF3T126MNR2G QFN−16
(Pb−Free)
3000/Tape & Ree
l
QFN−16
CASE 485G
1
NLSF3T126
http://onsemi.com
2
Figure 1. Logic Diagram
Active−High Output Enables
Y1
Y2
Y4
1
5
7
10
13
12
8
9
4
3
15
16
A1
OE1
A2
OE2
A3
OE3
A4
OE4
Y3
Figure 2. QFN − 16 Pinout (Top View)
Y2 GND Y3 A3
A1 OE1 V
CC
OE4
A4
Y4
Y1
NC
OE2
A2
NC
OE3
Exposed Pad (EP)
1
3
4
5678
9
10
11
12
13141516
2
MAXIMUM RATINGS
Rating Symbol Value Unit
DC Supply Voltage V
CC
–0.5 to +7.0 V
DC Input Voltage V
in
–0.5 to +7.0 V
DC Output Voltage Output in 3−State
High or Low State
V
out
–0.5 to +7.0
–0.5 to V
CC
+0.5
V
Input Diode Current I
IK
−20 mA
Output Diode Current (V
OUT
< GND; V
OUT
> V
CC
) I
OK
±20 mA
DC Output Current, per Pin I
out
±25 mA
DC Supply Current, V
CC
and GND Pins I
CC
±75 mA
Power Dissipation in Still Air, QFN Packages P
D
500 mW
Storage Temperature T
stg
–65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
DC Supply Voltage V
CC
2.0 5.5 V
DC Input Voltage V
in
0 5.5 V
DC Output Voltage Output in 3−State
High or Low State
V
out
0
0
5.5
V
CC
V
Operating Temperature T
A
−40 +85 °C
Input Rise and Fall Time V
CC
= 5.0 V ± 0.5 V t
r
, t
f
0 20 ns/V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
NLSF3T126
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Parameter Test Conditions
V
CC
(V)
T
A
= 25°C T
A
≤ 85°C T
A
≤ 125°C
Uni
t
Symbol Min Typ Max Min Max Min Max
Minimum
High−Level
Input Voltage
2.3 V ± 0.3 V
3.3 V ± 0.3 V
5.0 V ± 0.5 V
V
IH
0.5 V
CC
0.4 V
CC
0.44 V
CC
0.5 V
CC
0.4 V
CC
0.44 V
CC
0.5 V
CC
0.4 V
CC
0.44 V
CC
V
Maximum
Low−Level
Input Voltage
2.3 V ± 0.3 V
3.3 V ± 0.3 V
5.0 V ± 0.5 V
V
IL
0.3 V
CC
0.18 V
CC
0.18 V
CC
0.3 V
CC
0.18 V
CC
0.18 V
CC
0.3 V
CC
0.18 V
CC
0.18 V
CC
V
Minimum
High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
OL
@ I
OL
, 50 mA
V
IN
= V
IH
or V
IL
I
OH
= −50 mA
V
OH
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= −2.0 mA
I
OH
= −4.0 mA
I
OH
= −8.0 mA
2.0
3.0
4.5
1.82
2.58
3.94
1.72
2.48
3.80
1.60
2.34
3.66
Maximum
Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
OL
@ I
OL
, 50 mA
V
IN
= V
IH
or V
IL
I
OL
= 50 mA
V
OL
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 2.0 mA
I
OL
= 4.0 mA
I
OL
= 8.0 mA
2.0
3.0
4.5
0.36
0.36
0.36
0.44
0.44
0.44
0.52
0.52
0.52
Maximum
Input Leakage
Current
V
IN
= 5.5 V or GND I
IN
0
to
5.5
±0.1 ±1.0 ±1.0
mA
Maximum
Quiescent
Supply Current
V
IN
= V
CC
or GND I
CC
5.5 2.0 20 40
mA
Quiescent
Supply
Current
Input: V
IN
= 3.4 V I
CCT
5.5 1.35 1.50 1.65 mA
Maximum
3−State
Leakage
Current
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
I
OZ
5.5 ±0.25 ±2.5 ±2.5
mA
Output
Leakage
Current
V
OUT
= 5.5 V I
OPD
0.0 0.5 5.0 10
mA
P1-P3P4-P6

NLSF3T126MNR2

Mfr. #:
Buy NLSF3T126MNR2
Manufacturer:
ON Semiconductor
Description:
IC BUFFER NON-INVERT 5.5V 16QFN
Lifecycle:
New from this manufacturer.
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