DS2167Q Datasheet DS2167Q, DS2167QN, DS2167 | P4-P6

DS2167/DS2168

022698 4/15

HARDWARE MODE

The hardware mode is intended for preliminary system

prototyping or for applications which do not require the

features of the serial port. Tying SPS to VSS disables

the serial port, clears all internal registers and maps

IPD, µ/A

and CP/EX of the X and Y side interfaces to the

port and address inputs. Input and output timeslots for

the X and Y side interfaces are fixed at 0. Such applica-

tions include, but are not limited to: 1) systems in which

timeslot and algorithm are fixed, 2) stand-alone ADPCM

combo applications, 3) “hardware” oriented systems

where no host controller is available.

HARDWARE MODE Table 2

PIN #/NAME REG. LOCATION NAMES AND DESCRIPTION

4/A0 CP/EX (X) Channel X coding

0 = Expand

1 = Compress

6/A2 µ/A (X) Channel X data format

0 = A-law

1 = µ-law

7/A3 CP/EX (Y) Channel Y coding

0 = Expand

1 = Compress

9/A5 µ/A (Y).2 Channel Y data format

0 = A-law

1 = µ-law

18/SDI IPD (Y) Y idle select

0 = Channel active

1 = Channel idle

19/CS IPD (X) X idle select

0 = Channel active

1 = Channel idle

NOTES:

1. SCLK, A1 and A4 must be tied to VSS when the hardware mode is selected.

2. When both X and Y sides are idled, the devices enter a stand-by mode which significantly reduces power

consumption.

3. The DS2167 will power-up within 200 ms after the X or Y side is reactivated (SDI and/or CS

not equal to 0)

from standby.

4. The DS2168 must be hardware reset when reactivated from standby. Power-up occurs immediately after the

reset.

DS2167/DS2168

022698 5/15

CODEC/FILTER HARDWARE MODE INTERCONNECT Figure 2

CODEC/FILTER

DS2167/DS2167

TP3054 (µ-LAW)

TP3057 (µ-LAW)

TRANSMIT DATA

RECEIVE DATA

POWER DOWN

ACTIVE

10 MHz CLOCK

TRANSMIT FRAME SYNC

TRANSMIT DATA CLOCK

-5.0 V

RECEIVE DATA CLOCK

RECEIVE FRAME SYNC

TRANSMIT

ANALOG

INTERFACE

RECEIVE

ANALOG

INTERFACE

POWER ON RESET

(DS1231)

VCC

VBB

GNDA

TSX

VFXI+

VFSI-

GSX

VFRO

MCLKX

FSX

BCLKX

FSR

BCLK/

CLKSEL

MCLK/PDN

RST

SCLK

XIN

FSX

CLKX

YOUT

FSY

CLKY

TM0

TM1

VSS

SPS

VDD

XOUT

YIN

SDI

MCLK

NOTE:

Suggested Codec/Filters

TP305X National Semiconductor

ETC505X SGS–Thomson Microelectronics

MC1455XX Motorola

TCM29CXX Texas Instruments

HD44238C Hitachi

*other generic Codec/Filter devices can be substituted.

SOFTWARE MODE

Tying SPS high enabled the software mode. In this

mode, a host microcontroller writes configuration data

to the DS2167/DS2168 serial port via inputs SCLK, SDI,

and CS

. Independent control and timeslot registers es-

tablish operating characteristics for the X-side and Y-

side PCM interfaces.

ADDRESS/COMMAND BYTE

In the software mode, the address/command byte is the

first byte written to the serial port; it identifies which of 64

possible ADPCM processors sharing the port wiring is

to be updated. Address data must match that at inputs

A0–A5. If no match occurs, the device ignores the fol-

lowing configuration data. If an address match occurs,

the next three bytes written are accepted as control, in-

put and output timeslot data. Bit ACB.6 determines

which side (X or Y) of the device is to be updated.

CONTROL REGISTER

The control register establishes idle, algorithm reset,

bypass, data format and channel coding for the selected

PCM interface.

The X and Y side PCM interfaces may be independently

disabled (output tri-stated) via IPD; when IPD is set for

DS2167/DS2168

022698 6/15

both X and Y interfaces, the device enters a low-power

standby mode. The DS2167 will power-up within

200 ms after the X or Y side is reactivated (IPD=0) from

standby. The DS2168 requires an external hardware re-

set after IPD is cleared to “wake-up” from standby. The

DS2168 will power-up immediately after the low-high

transition on RST

ALRST resets the algorithm coefficients for the selected

channel to their initial values. ALRST will be cleared by

the device when the algorithm reset is complete.

The bypass feature is enabled when BYP is set and IPD

is clear. During bypass, no expansion or compression of

data occurs. This feature allows the user to interchange

timeslots under control of the timeslot registers. Bypass

operates on byte-wide slots when CP/EX

=1, on nibble-

wide slots when CP/EX

=0.

A-law (µ/A

=0) or µ-law PCM (µ/A=1) coding is indepen-

dently selected for the X and Y side interfaces by bit µ/A.

If BYP and IPD are clear, CP/EX

determines if input data

is to be compressed or expanded.

TIMESLOT ASSIGNMENT

On-chip counters establish when PCM data I/O occurs

and are programmed via the timeslot registers. Timeslot

size (4 or 8 bits wide) is determined by the state of

CP/EX

. Timeslots are counted from the rising edge of

FSX and FSY.

ADDRESS/COMMAND BYTE Figure 3

(MSB) (LSB)

–

X/Y A5 A4 A3 A2 A1 a0

SYMBOL POSITION NAME AND DESCRIPTION

– ACB.7 Reserved, must be 0 for proper operation.

X/Y

ACB.6 X/Y Channel Select.

0 = Update channel Y characteristics.

1 = Update channel X characteristics.

A5 ACB.5 MSB of Device Address.

A4 ACB.4

A3 ACB.3

A2 ACB.2

A1 ACB.1

A0 ACB.0 LSB of Device Address.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

DS2167Q

Mfr. #:

Buy DS2167Q

Manufacturer:

Maxim Integrated

Description:

IC PROC ADPCM 16/24/32K 28-PLCC

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DS2167Q

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