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74ACTQ563PC

P1-P3P4-P6P7-P7
January 1990
Revised December 1998
74ACTQ563 Quiet Series Octal Latch with 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS010631.prf www.fairchildsemi.com
74ACTQ563
Quiet Series Octal Latch with 3-STATE Outputs
General Description
The ACTQ563 is a high speed octal latch with buffered
common Latch Enable (LE) and buffered common Output
Enable (OE
) inputs. The ACTQ563 is functionally identical
to the ACTQ573, but with inverted outputs. The ACTQ563
utilizes Fairchild FACT Quiet Series technology to guar-
antee quiet output switching and improved dynamic thresh-
old performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
Features
■ I
CC
and I
OZ
reduced by 50%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
■ Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
■ Outputs source/sink 24 mA
■ Faster prop delays than standard ACT563
■ Functionally identical to the ACTQ573 but with inverted
outputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Assignment for DIP
Pin Descriptions
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ563PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE
3-STATE Output Enable Input
O
0
–O
7
3-STATE Latch Outputs
www.fairchildsemi.com 2
74ACTQ563
Functional Description
The ACTQ563 contains eight D-type latches with 3-STATE
complementary outputs. When the Latch Enable (LE) input
is HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The 3-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers
are in the bi-state mode. When OE
is HIGH the buffers are
in the high impedance mode but that does not interfere with
entering new data into the latches.
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Internal Outputs Function
OE
LE D Q O
H X X X Z High-Z
H H L H Z High-Z
H H H L Z High-Z
H L X NC Z Latched
L H L H H Transparent
L H H L L Transparent
L L X NC NC Latched
3 www.fairchildsemi.com
74ACTQ563
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
) ± 50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ± 50 mA
Storage Temperature (T
STG
) −65°C to +150°C
DC Latchup Source
or Sink Current ± 300 mA
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (V
O
)0V to V
CC
Operating Temperature (T
A
) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol Parameter
V
CC
T
A
= +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or V
CC
− 0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or V
CC
− 0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4 V I
OUT
= − 50 µA
Output Voltage 5.5 5.49 5.4 5.4
V
IN
= V
IL
or V
IH
4.5 3.86 3.76 V I
OH
= −24 mA
5.5 4.86 4.76 I
OH
= − 24 mA (Note 2)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1 I
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
V
IN
= V
IL
or V
IH
4.5 0.36 0.44 V I
OL
= 24 mA
5.5 0.36 0.44 I
OL
= 24 mA (Note 2)
I
IN
Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAV
I
= V
CC
, GND
I
OZ
Maximum 3-STATE 5.5 ± 0.25 ± 2.5 µAV
I
= V
IL
, V
IH
Leakage Current V
O
= V
CC
, GND
I
CCT
Maximum I
CC
/Input 5.5 0.6 1.5 mA V
I
= V
CC
− 2.1V
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent Supply Current 5.5 4.0 40.0 µAV
IN
= V
CC
or GND
V
OLP
Quiet Output 5.0 1.1 1.5 V Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 4)(Note 5)
V
OLV
Quiet Output 5.0 −0.6 −1.2 V Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 4)(Note 5)
V
IHD
Minimum HIGH Level
Dynamic Input Voltage
5.0 1.9 2.2 V (Note 4)(Note 6)
V
ILD
Maximum LOW Level
Dynamic Input Voltage
5.0 1.2 0.8 V (Note 4)(Note 6)
P1-P3P4-P6P7-P7

74ACTQ563PC

Mfr. #:
Buy 74ACTQ563PC
Manufacturer:
ON Semiconductor / Fairchild
Description:
Latches Octal Latch
Lifecycle:
New from this manufacturer.
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