18
LTC1414
Digital Interface
The A/D converter has just one control input CONVST.
Data is output on 14-bit parallel bus. An additional output
BUSY indicates the converter status.
DIGITAL OUTPUTS
The parallel digital outputs of the LTC1414 are designed to
interface to TTL and CMOS logic. The output data is two’s
complement coded.
The output drivers have a separate power pin (OV
DD
) and
ground pin (OGND). This allows relatively noisy output
ground and the output supply bypass ground to be sepa-
rated from the other ADC grounds. Additionally, the OV
DD
pin may be driven by the supply of the logic that is being
driven. For example, the OV
DD
supply may be 3V while
LTC1414 DV
DD
and AV
DD
pins are 5V, allowing 3V logic to
be driven directly.
Care should be taken to not load the digital outputs with
excessive capacitance. Large capacitive loads result in
large charging currents which can cause conversion er-
rors. It is recommended that the capacitive loading is kept
under 20pF. If it is not possible to keep the capacitance
low, a buffer or latch may be used to isolate the LTC1414
from the capacitive load.
Timing and Control
The conversion start is controlled by the CONVST input.
The falling edge of CONVST will start a conversion. Once
initiated, it cannot be restarted until the conversion is
complete. Converter status is indicated by the BUSY
output. BUSY is low during a conversion.
APPLICATIONS INFORMATION
WUU
U
The output data is updated at the end of the conversion as
BUSY rises. Output data is updated coincident with the
rising edge of BUSY. Data will be valid, and can be latched,
20ns after the rising edge of BUSY. Valid data can also be
latched with the falling edge of BUSY or with the rising
edge of CONVST. In the latter two cases the data latched
will be for the previous conversion.
CONVST Drive Considerations
Timing jitter of the CONVST signal can adversely affect the
noise performance of the LTC1414 when the input signal
contains high slew rate components. The falling edge of
CONVST determines the sampling instant. Any uncer-
tainty in this sampling instant will translate to voltage
noise when a fast changing input signal is being sampled.
For a full amplitude sinusoidal input, the relationship
between timing jitter (t
jitter
) and SNR
j
is
SNR
j
= 20log(1/2π • f
IN
• t
jitter
)
where SNR
j
is the signal-to-jitter noise ratio.
The internal circuitry of the LTC1414 has been optimized
for ultralow jitter (typically 3ps RMS). The external clock
drive circuitry is equally important and must also have low
jitter to achieve low noise.
Internal Clock
The internal clock is factory trimmed to achieve a typical
conversion time of 330ns and a maximum conversion
time over the full operating temperature range of 400ns.
No external adjustments are required. The guaranteed
maximum acquisition time is 100ns. In addition, a through-
put time (acquisition + conversion) of 454ns and a mini-
mum sampling rate of 2.2Msps is guaranteed.
Figure 17. Timing Diagram
DATA (N – 1)
DB13 TO DB0
CONVST
BUSY
1414 F17
t
4
t
5
t
CONV
t
1
t
3
t
2
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA
