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TSL2581CS-DB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134 − MARCH 2011
13
The LUMENOLOGY r Company
r
r
Copyright E 2011, TAOS Inc.
www.taosinc.com
Table 8. Interrupt Persistence Select
PERSIST FIELD VALUE INTERRUPT PERSIST FUNCTION
0000 Every ADC cycle generates interrupt
0001 Any value outside of threshold range
0010 2 integration time periods out of range
0011 3 integration time periods out of range
0100 4 integration time periods out of range
0101 5 integration time periods out of range
0110 6 integration time periods out of range
0111 7 integration time periods out of range
1000 8 integration time periods out of range
1001 9 integration time periods out of range
1010 10 integration time periods out of range
1011 11 integration time periods out of range
1100 12 integration time periods out of range
1101 13 integration time periods out of range
1110 14 integration time periods out of range
1111 15 integration time periods out of range
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134 − MARCH 2011
14
r
r
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
Interrupt Threshold Registers (03h − 06h)
The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison
function for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low
threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses
above the high threshold specified, an interrupt is asserted on the interrupt pin. Registers TLLOW and
TLHIGH provide the low byte and high byte, respectively, of the lower interrupt threshold. Registers THLOW
and THHIGH provide the low and high bytes, respectively, of the upper interrupt threshold. The high and low
bytes from each set of registers are combined to form a 16-bit threshold value. The interrupt threshold registers
default to 00h on power up.
Table 9. Interrupt Threshold Registers
REGISTER ADDRESS BITS DESCRIPTION
TLLOW 3h 7:0 ADC channel 0 lower byte of the low threshold
TLHIGH 4h 7:0 ADC channel 0 upper byte of the low threshold
THLOW 5h 7:0 ADC channel 0 lower byte of the high threshold
THHIGH 6h 7:0 ADC channel 0 upper byte of the high threshold
NOTE: Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the Send Byte protocol should
not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted as the
COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desired.
The Write Word protocol should be used to write byte-paired registers. For example, the TLLOW and TLHIGH registers (as well as the
THLOW and THHIGH registers) can be written together to set the 16-bit ADC value in a single transaction.
Analog Register (07h)
The ANALOG register provides eight bits of control to the analog block. These bits control the analog gain
settings of the device.
Table 10. Analog Register
67542310
RESV GAIN
Address
07h
Reset
00h
Bit :
FIELD BITS DESCRIPTION
Resv 7:3 Reserved. Write as 0.
Gain Control. Sets the analog gain of the device according to the following table.
FIELD VALUE GAIN VALUE
Gain
2:0
x00 1×
Gain 2:0
x01 8×
x10 16×
x11 111×
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134 − MARCH 2011
15
The LUMENOLOGY r Company
r
r
Copyright E 2011, TAOS Inc.
www.taosinc.com
ID Register (12h)
The ID register provides the value for both the part number and silicon revision number for that part number.
It is a read-only register whose value never changes.
Table 11. ID Register
6754
REVNO
2310
PARTNO
Address
12h
Reset
− −
Bit :
FIELD BITS DESCRIPTION
PARTNO 7:4 Part Number Identification: field value 1001b
REVNO 3:0 Revision number identification
ADC Channel Data Registers (14h − 17h)
The ADC channel data are expressed as 16-bit values spread across two registers. The ADC channel 0 data
registers, DATA0LOW and DATA0HIGH provide the lower and upper bytes, respectively, of the ADC value of
channel 0. Registers DATA1LOW and DATA1HIGH provide the lower and upper bytes, respectively, of the ADC
value of channel 1. All channel data registers are read-only and default to 00h on power up.
Table 12. ADC Channel Data Registers
REGISTER ADDRESS BITS DESCRIPTION
DATA0LOW 14h 7:0 ADC channel 0 lower byte
DATA0HIGH 15h 7:0 ADC channel 0 upper byte
DATA1LOW 16h 7:0 ADC channel 1 lower byte
DATA1HIGH 17h 7:0 ADC channel 1 upper byte
The upper byte data registers can only be read following a read to the corresponding lower byte register. When
the lower byte register is read, the upper eight bits are strobed into a shadow register, which is read by a
subsequent read to the upper byte. The upper register will read the correct value even if additional ADC
integration cycles end between the reading of the lower and upper registers.
NOTE: The Read Word protocol can be used to read byte-paired registers. For example, the DATA0LOW and DATA0HIGH registers (as well as
the DATA1LOW and DATA1HIGH registers) may be read together to obtain the 16-bit ADC value in a single transaction
Manual Integration Timer Registers (18h − 19h)
The MANUAL INTEGRATION TIMER registers provide the number of cycles in 10.9 μs increments that
occurred during a manual start/stop integration period. The timer is expressed as a 16-bit value across two
registers. See CONTROL and TIMING Registers for further instructions in configuring a manual integration.
The maximum time that can be derived without an overflow is 714.3 ms.
Table 13. Manual Integration Timer Registers
67542310
TIMER
Address
18h 19h
Reset
00h
Bit :
REGISTER ADDRESS BITS DESCRIPTION
TIMERLOW 18h 7:0 Manual Integration Timer lower byte
TIMERHIGH 19h 7:0 Manual Integration Timer upper byte
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

TSL2581CS-DB

Mfr. #:
Buy TSL2581CS-DB
Manufacturer:
ams
Description:
Optical Sensor Development Tools Daughter Board for the TSL2581CS
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New from this manufacturer.
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