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TSL2583CS

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134 − MARCH 2011
7
The LUMENOLOGY r Company
r
r
Copyright E 2011, TAOS Inc.
www.taosinc.com
PRINCIPLES OF OPERATION
Analog-to-Digital Converter
The TSL258x contains two integrating analog-to-digital converters (ADC) that integrate the currents from the
channel 0 and channel 1 photodiodes. Integration of both channels occurs simultaneously, and upon completion
of the conversion cycle the conversion result is transferred to the channel 0 and channel 1 data registers,
respectively. The transfers are double buffered to ensure that invalid data is not read during the transfer. After
the transfer, the device automatically begins the next integration cycle.
Digital Interface
Interface and control of the TSL258x is accomplished through a two-wire serial interface to a set of registers
that provide access to device control functions and output data. The serial interface is compatible with I
2
C bus
Fast-Mode. The TSL258x offers three slave addresses that are selectable via an external pin (ADDR SEL). The
slave address options are shown in Table 1.
Table 1. Slave Address Selection
ADDR SEL TERMINAL LEVEL SLAVE ADDRESS
GND 0101001
Float 0111001
V
DD
1001001
NOTE: A read/write bit should be appended to the slave address by the master device to properly communicate with the TSL258x device.
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134 − MARCH 2011
8
r
r
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
I
2
C Protocol
Interface and control are accomplished through an I
2
C serial compatible interface (standard or fast mode) to
a set of registers that provide access to device control functions and output data. The devices support the 7-bit
I
2
C addressing protocol.
The I
2
C standard provides for three types of bus transaction: read, write, and a combined protocol (Figure 4).
During a write operation, the first byte written is a command byte followed by data. In a combined protocol, the
first byte written is the command byte followed by reading a series of bytes. If a read command is issued, the
register address from the previous command will be used for data access. Likewise, if the MSB of the command
is not set, the device will write a series of bytes at the address stored in the last valid command with a register
address. The command byte contains either control information or a 5-bit register address. The control
commands can also be used to clear interrupts.
The I
2
C bus protocol was developed by Philips (now NXP). For a complete description of the I
2
C protocol, please
review the NXP I
2
C design specification at http://www.i2c−bus.org/references/.
A Acknowledge (0)
N Not Acknowledged (1)
P Stop Condition
R Read (1)
S Start Condition
Sr Repeated Start Condition
W Write (0)
... Continuation of protocol
Master-to-Slave
Slave-to-Master
W
7
Data ByteSlave AddressS
1
AAA
811 1 8
Command Code
1
P
1
...
I
2
C Write Protocol
I
2
C Read Protocol
I
2
C Read Protocol — Combined Format
R
7
DataSlave AddressS
1
AAA
811 1 8
Data
1
P
1
...
W
7
Slave AddressSlave AddressS
1
ARA
811 1 7 11
Command Code
Sr
1
A
Data AA
81 8
Data
1
P
1
...
Figure 4. I
2
C Protocols
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134 − MARCH 2011
9
The LUMENOLOGY r Company
r
r
Copyright E 2011, TAOS Inc.
www.taosinc.com
Register Set
The TSL258x is controlled and monitored by sixteen registers and a command register accessed through the
serial interface. These registers provide for a variety of control functions and can be read to determine results
of the ADC conversions. The register set is summarized in Table 2.
Table 2. Register Address
ADDRESS RESISTER NAME REGISTER FUNCTION R/W
−− COMMAND Specifies register address W
00h CONTROL
Control of basic functions
01h TIMING
Integration time/gain control
02h INTERRUPT
Interrupt control
03h TLLOW
Low byte of low interrupt threshold
R/W
04h TLHIGH
High byte of low interrupt threshold
R/W
05h THLOW
Low byte of high interrupt threshold
06h THHIGH
High byte of high interrupt threshold
07h ANALOG
Analog control register
12h ID
Part number / Rev ID
14h DATA0LOW
ADC channel 0 LOW data register
15h DATA0HIGH
ADC channel 0 HIGH data register
16h DATA1LOW
ADC channel 1 LOW data register
R
17h DATA1HIGH
ADC channel 1 HIGH data register
R
18h TIMERLOW
Manual integration timer LOW register
19h TIMERHIGH
Manual integration timer HIGH register
1Eh ID2 TSL2581 / TSL2583 ID R/W
The mechanics of accessing a specific register is given in the I
2
C Protocol section. In general, the COMMAND
register is written first to specify the specific control/status register for following read/write operations.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

TSL2583CS

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Buy TSL2583CS
Manufacturer:
ams
Description:
Light to Digital Converters LTD 30x Sens I2C Chipscale 3V
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