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ISL88042IRTEEZ-T

P1-P3P4-P6P7-P8
4
FN6655.2
July 26, 2010
Pin Descriptions
RST
The RST output is an open drain output, which is asserted
low whenever the following occurs:
1. The device is initially powered up to 1V or
2. V
DD
, V2MON, V3MON or V4MON fall below their
minimum voltage sense level.
MR
The MR input is an active low debounced input to which a
user can connect a push-button to add manual reset
capability or use a signal to pull low. MR
has an internal
pull-up resistor.
V
DD
The V
DD
pin is the IC power supply terminal. The voltage at
this pin is compared against an internal factory-programmed
voltage trip point, V
TH1
. RST is first asserted low when the
device is initially powered and V
DD
< 1V and then at any
time thereafter when V
DD
falls below V
TH1
. The device is
designed with hysteresis to help prevent chattering due to
noise and is immune to brief power-supply transients.
V2MON
The V2MON input is the second preset monitored voltage
that causes the RST
output to go low when the voltage on
V2MON falls below V
TH2
.
V3MON, and V4MON
The VxMON inputs provide monitoring and UV compliance
of three additional voltages through resistor dividers. A reset
is issued on the ISL88042 if the voltage on any VxMON falls
below the internal V
REF
of 0.6V.
.
Principles of Operation
The ISL88042 device provides those functions needed for
monitoring critical voltages, such as power-supply and battery
functions in microprocessor systems. It provides such features
as Power-On Reset control, supply voltage supervision, and
Manual Reset Assertion. The integration of all these features
along with competitive reset threshold accuracy and low power
consumption, makes the ISL88042 device suitable for a wide
variety of applications needing multi-voltage monitoring. See
Figure 1 for the “Typical Application Diagram”.
Low Voltage Monitoring
During normal operation, the ISL88042 monitors the voltage
levels of V
DD
, V2MON, V3MON and V4MON. If the voltage on
any of these four inputs falls below their respective voltage trip
points, a reset is asserted (RST
= low) to prevent the
microprocessor from operating during a power failure or
brownout condition. This reset signal remains low until the
voltages exceeds the voltage threshold settings for the reset
time delay period t
POR
.
The ISL88042 allows users to customize the minimum voltage
sense level for two of the four monitored voltages. For example,
the user can adjust the voltage input trip point (V
TRIP
) for the
V3MON and V4MON inputs. To do this, connect an external
resistor divider network to the VxMON pin in order to set the trip
MANUAL RESET
V
MRL
MR Input Voltage Low 0.8 V
V
MRH
MR Input Voltage High V
DD
- 0.6 V
t
MR
MR Minimum Pulse Width 550 ns
R
PU
Internal Pull-Up Resistor 10 kΩ
NOTE:
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 5) TYP
MAX
(Note 5) UNITS
FIGURE 1. TYPICAL APPLICATION DIAGRAM
V2MON
MR
PB
GND
RST
RESET
V
DD
ISL88042
SIGNAL
V3MON
V4MON
ISL88042
5
FN6655.2
July 26, 2010
point to some other voltage above 600mV according to
Equation 1:
Power-On Reset (POR)
Applying power to the ISL88042 activates a POR circuit, which
makes the reset pin(s) active (i.e. RST goes high while RST
goes low). These signals provide several benefits:
• They prevent the system microprocessor from starting to
operate with insufficient voltage.
• They prevent the processor from operating prior to
stabilization of the oscillator.
• They ensure that the monitored device is held out of
operation until internal registers are properly loaded.
• They allow time for an FPGA to download its configuration
prior to initialization of the circuit.
The reset signal remains active until V
DD
rises above the
minimum voltage sense level for time period t
POR
. This
ensures that the supply voltage has stabilized to sufficient
operating levels.
Manual Reset
The manual-reset input (MR) allows the user to trigger a reset
by using a push-button switch or by signaling the input low. The
MR
input is an active low debounced input. Reset is asserted if
the MR
pin is pulled low to less than 100mV for the minimum
MR
pulse width or longer while the push-button is closed. After
MR
is released, the reset output remains asserted low for t
POR
(200ms) and then is released.
Figures 2 and 3 illustrate the ISL88042’s operation.
V
TRIP
0.6V= R
1
R
2
/+× R
2
(EQ. 1)
V
DD /
V2MON
MR
RST
t
POR
V
TH1/
V
TH2
1V
t
POR
t
POR
>t
MR
t
RPD
FIGURE 2. POWER SUPPLY MONITORING DIAGRAM
>t
MD
VXMON
RST
V
TH
t
POR
t
RPD
FIGURE 3. VOLTAGE MONITORING DIAGRAM
ISL88042
6
FN6655.2
July 26, 2010
The ISL88042EVAL1Z and Applications
The ISL88042EVAL1Z supports all variants of the ISL88042
devices, enabling evaluation of basic functional operation and
common application implementations. Figure 10 illustrates the
ISL88042EVAL1Z in schematic and photographic forms. The
ISL88042EVAL1Z is populated with the ISL88042IRTEEZ
(V
DD
V
TH1
and V2MON V
TH2
=2.90V).
With adequate bias on the two preset and the two adjustable
monitor inputs the RST
output will release to pull high
indicating that all supplies are compliant for a minimum of
t
POR
. For the ISL88042EVAL1Z as shipped, the V
DD
and
V2MON nominal thresholds are as previously noted with the
voltage thresholds being monitored by V3MON and V4MON
being left open for programming via the non populated
resistor dividers.
Special Application Considerations
Using good decoupling practices on bias and other
monitoring inputs will prevent transients (i.e. due to switching
noises and short duration droops in the supply voltage) from
causing unwanted resets.
In unusually noisy environments or situations where
unwanted signals may be injected into the adjustable VMON
inputs, lowering the node impedance and/or positioning a
small valued filter capacitor as close to the pin as possible
can increase noise immunity.
Although the internal ISL88042 threshold references are
guaranteed over the full temp range, accuracy errors due to
external component tolerances and distribution losses will
occur. High tolerance resistors and layout for extreme
accuracy and critical performance must be considered.
Typical Performance Curves
FIGURE 4. VDD and V2MON Vth vs TEMPERATURE
FIGURE 5. V3MON and V4MON Vth vs TEMPERATURE
FIGURE 6. t
por
vs TEMPERATURE
FIGURE 7. BIAS CURRENT vs TEMPERATURE
3.20
3.15
3.10
3.00
2.95
2.90
2.85
2.80
2.75
2.70
3.05
4.60
4.59
4.58
4.56
4.55
4.54
4.53
4.57
-40 -20 0 25 50 85 100 125
TEMPERATURE (°)
ISL88042IRTHF VDD
ISL88042IRTHF V2MON
ISL88042IRTEE V2MON
ISL88042IRTEE VDD
ISL88042IRTJJ V2MON
ISL88042IRTJJ VDD
VDD & V2MON Vth (V)
610
605
600
595
590
585
580
575
570
-40 -20 0 25 50 85 100 125
TEMPERATURE (°C)
VXMON Vth (mV)
ISL88042IRTHF ISL88042IRTEE V4MON
ISL88042IRTHF ISL88042IRTEE V3MON
ISL88042IRTJJ V4MON
ISL88042IRTJJ V3MON
80
85
90
95
100
105
110
115
120
-40-200 255085100125
TEMPERATURE (°C)
t
POR
(ms)
0
2
4
6
8
10
12
14
16
-40 -20 0 25 50 85 100 125
TEMPERATURE (°C)
BIAS CURRENT (µA)
VDD = 5V
V2MON = 3.3V
ISL88042
P1-P3P4-P6P7-P8

ISL88042IRTEEZ-T

Mfr. #:
Buy ISL88042IRTEEZ-T
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits QDRUPLE VAGE MONITOR 2 90V 8LD 2X3
Lifecycle:
New from this manufacturer.
Delivery:
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