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ADV7181CBSTZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet ADV7181C
Rev. E | Page 9 of 20
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD to AGND 4 V
DVDD to DGND 2.2 V
PVDD to AGND 2.2 V
DVDDIO to DGND 4 V
DVDDIO to AVDD −0.3 V to +0.3 V
PVDD to DVDD −0.3 V to +0.3 V
DVDDIO to PVDD −0.3 V to +2 V
DVDDIO to DVDD
−0.3 V to +2 V
AVDD to PVDD −0.3 V to +2 V
AVDD to DVDD −0.3 V to +2 V
Digital Inputs Voltage to DGND DGND − 0.3 V to
DVDDIO + 0.3 V
Digital Outputs Voltage to DGND DGND − 0.3 V to
DVDDIO + 0.3 V
Analog Inputs to AGND AGND − 0.3 V to
AVDD + 0.3 V
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature (T
J MAX
) 125°C
Storage Temperature Range −65°C to +150°C
Infrared Reflow, Soldering (20 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the part, turn off any
unused ADCs.
It is imperative that the recommended scripts be used for the
following high current modes: SCART, 720p, 1080i, and all
RGB graphic standards. Using the recommended scripts ensures
correct thermal performance. These scripts are available from
a local FAE.
The junction temperature must always stay below the maximum
junction temperature (T
J
MAX
) of 125°C. The junction temperature
can be calculated by
T
J
= T
A MAX
+ (θ
JA
× W
MAX
)
where:
T
A MAX
= 85°C.
θ
JA
= 45.5° C / W.
W
MAX
= ((AVDD × IAVDD) + (DVDD × IDVDD) +
(DVDDIO × IDVDDIO) + (PVDD × IPVDD)).
THERMAL SPECIFICATIONS
Table 6.
Parameter Test Conditions Value
Junction-to-Case
Thermal Resistance, θ
JC
4-layer PCB with solid
ground plane
9.2°C/W
typical
Junction-to-Ambient
Thermal Resistance, θ
JA
4-layer PCB with solid
ground plane (still air)
45.5°C/W
typical
ESD CAUTION
ADV7181C Data Sheet
Rev. E | Page 10 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
VS
63
FIELD/DE
62
P16
61
P17
60
P18
59
P19
58
DVDD
57
DGND
56
HS_IN/CS_IN
55
VS_IN
54
SCLK
53
SDATA
52
ALSB
51
RESET
50
SOG/SOY
49
A
IN
6
47
A
IN
4
46
A
IN
3
45
NC
42
CML
43
AGND
44
CAPC2
48
A
IN
5
41
REFOUT
40
AVDD
39
CAPY2
37
AGND
36
A
IN
2
35
A
IN
1
34
FB
33
NC
38
CAPY1
2
HS/CS
3
DGND
4
DVDDIO
7
P13
6
P14
5
P15
1
INT
8
P12
9
SFL/SYNC_OUT
10
DGND
12
P11
13
P10
14
P9
15
P8
16
P7
11
DVDDIO
17
P6
18
P5
19
P4
20
LLC
21
XTAL1
22
XTAL
23
DVDD
24
DGND
25
P3
26
P2
27
P1
28
P0
29
PWRDWN
30
ELPF
31
PVDD
32
AGND
PIN 1
ADV7181C
TOP VIEW
(Not to Scale)
07513-002
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1
INT
O Interrupt. This pin can be active low or active high. When SDP/CP status bits
change, this pin is triggered. The set of events that triggers an interrupt is
under user control.
2 HS/CS O HS: Horizontal Synchronization Output Signal (SDP and CP Modes).
CS: Digital Composite Synchronization Signal (CP Mode).
3, 10, 24, 57 DGND G Digital Ground.
4, 11 DVDDIO P Digital I/O Supply Voltage (3.3 V).
28 to 25, 19 to 12, 8 to 5,
62 to 59
P0 to P19 O Video Pixel Output Port. Refer to Table 10 for output configuration modes.
9 SFL/SYNC_OUT O SFL: Subcarrier Frequency Lock. This pin contains a serial output stream that
can be used to lock the subcarrier frequency when this decoder is connected
to any Analog Devices digital video encoder.
SYNC_OUT: Sliced Synchronization Output Signal Available Only in CP Mode.
20 LLC O Line-Locked Output Clock. This pin is for the pixel data (the range is
12.825 MHz to 110 MHz).
21 XTAL1 O This pin should be connected to the 28.63636 MHz crystal or left as a no connect
if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the
ADV7181C. In crystal mode, the crystal must be a fundamental crystal.
22 XTAL I Input pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,
28.63636 MHz clock oscillator source to clock the ADV7181C.
23, 58 DVDD P Digital Core Supply Voltage (1.8 V).
29
PWRDWN
I A Logic 0 on this pin places the ADV7181C in a power-down mode.
30 ELPF O The recommended external loop filter must be connected to this ELPF pin.
31 PVDD P PLL Supply Voltage (1.8 V).
32, 37, 43 AGND G Analog Ground.
Data Sheet ADV7181C
Rev. E | Page 11 of 20
Pin No. Mnemonic Type
1
Description
33, 45 NC No Connect. These pins are not connected internally.
34 FB I Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
35, 36, 46, 47, 48, 49 A
IN
1 to A
IN
6 I Analog Video Input Channels.
38, 39 CAPY1, CAPY2 I ADC Capacitor Network. See Figure 9 for a recommended capacitor network
for this pin.
40 AVDD P Analog Supply Voltage (3.3 V).
41 REFOUT O Internal Voltage Reference Output. See Figure 9 for a recommended capacitor
network for this pin.
42 CML O Common-Mode Level Pin (CML) for the Internal ADCs. See Figure 9 for a
recommended capacitor network for this pin.
44 CAPC2 I ADC Capacitor Network. See Figure 9 for a recommended capacitor network
for this pin.
50 SOG/SOY I Sync on Green/Sync on Luma Input. Used in embedded synchronization mode.
51
RESET
I System Reset Input, Active Low. A minimum low reset pulse width of 5 ms
is required to reset the ADV7181C circuitry.
52 ALSB I This pin selects the I
2
C address for the ADV7181C control and VBI readback
ports. ALSB set to Logic 0 sets the address for a write to Control Port 0x40 and
the readback address for VBI Port 0x21. ALSB set to a Logic 1 sets the address
for a write to Control Port 0x42 and the readback address for VBI Port 0x23.
53 SDATA I/O I
2
C Port Serial Data Input/Output Pin.
54 SCLK I I
2
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
55
VS_IN
I
VS Input Signal. Used in CP mode for 5-wire timing mode.
56 HS_IN/CS_IN I This pin can be configured in CP mode to be either a digital HS input signal or
a digital CS input signal used to extract timing in a 5-wire or 4-wire RGB mode.
63 FIELD/DE O Field Synchronization Output Signal (All Interlaced Video Modes). This pin
also can be enabled as a data enable signal (DE) in CP mode to allow direct
connection to a HDMI/DVI Tx IC.
64 VS O Vertical Synchronization Output Signal (SDP and CP Modes).
1
G = ground, I = input, O = output, I/O = input/output, and P = power.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADV7181CBSTZ-REEL

Mfr. #:
Buy ADV7181CBSTZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10B Intg Multiformat SDTV/HDTV
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