AD7720
–6–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1 REF2 Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used
to drive the sigma-delta modulator. When REF2 is used as an input, REF1 must be con-
nected to AGND.
2, 14, 18, 20, 24, 26 AGND Ground reference point for analog circuitry.
3, 13 NC No Connect.
4 STBY Standby, Logic Input. When STBY is high, the device is placed in a low power mode.
When STBY is low, the device is powered up.
5 DVAL Data Valid Logic Output. A logic high on DVAL indicates that the data bit stream from
the AD7720 is an accurate digital representation of the analog voltage at the input to the
sigma-delta modulator. The DVAL pin is set low for 20 MCLK cycles if the analog input is
overranged.
6, 15 DGND Ground reference for the digital circuitry.
7 GC Digital Control Input. When GC is high, the gain error of the modulator can be calibrated.
8 BIP Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A
logic high selects bipolar mode.
9 MZERO Digital Control Input. When MZERO is high, the modulator inputs are internally grounded,
i.e., tied to AGND in unipolar mode and REF2 in bipolar mode. MZERO allows on-chip
offsets to be calibrated out. MZERO is low for normal operation.
10 DATA Modulator Bit Stream. The digital bit stream from the sigma-delta modulator is output at
DATA.
11 SCLK Serial Clock, Logic Output. The bit stream from the modulator is valid on the rising edge
of SCLK.
12 RESETO Reset Logic Output. The signal applied to the RESET pin is made available as an output at
RESETO.
16 XTAL1/MCLK CMOS Logic Clock Input. The XTAL1/MCLK pin interfaces the device’s internal oscillator
circuit to an external crystal or an external clock. A parallel resonant, fundamental-frequency,
microprocessor-grade crystal and a 1 M resistor should be connected between the MCLK
and XTAL pins with two capacitors connected from each pin to ground. Alternatively, the
XTAL1/MCLK pin can be driven with an external CMOS-compatible clock. The part is
specified with a 12.5 MHz master clock.
17 XTAL2 Oscillator Output. The XTAL2 pin connects the internal oscillator output to an external
crystal. If an external clock is used, XTAL2 should be left unconnected.
19 DVDD Digital Supply Voltage, +5 V ± 5%.
21, 23 VIN(–), VIN(+) Analog Input. In unipolar operation, the analog input range on VIN(+) is VIN(–) to
(VIN(–) + V
REF
); for bipolar operation, the analog input range on VIN+ is (VIN(–) ± V
REF
/2).
The absolute analog input range must lie between 0 and AVDD. The analog input is con-
tinuously sampled and processed by the analog modulator.
25, 28 AVDD Analog Positive Supply Voltage, +5 V ± 5%.
22 RESET Reset Logic Input. RESET is an asynchronous input. When RESET is taken high, the
sigma-delta modulator is reset by shorting the integrator capacitors in the modulator. DVAL
goes low for 20 MCLK cycles while the modulator is being reset.
27 REF1 Reference Input/Output. REF1 connects via a 3 k resistor to the output of the internal
2.5 V reference, and to the input of a buffer amplifier that drives the sigma-delta modulator.
This pin can also be overdriven with an external 2.5 V reference.
AD7720
–7–REV. 0
TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7720
[FIGURE 1])
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con-
fused with bipolar zero), a point 0.5 LSB below the first code
transition (100...00 to 100...01 in bipolar mode and
000...00 to 000...01 in unipolar mode) and full scale, a
point 0.5 LSB above the last code transition (011...10 to
011...11 in bipolar mode and 111...10 to 111...11 in
unipolar mode). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between two adjacent codes in the ADC.
Common-Mode Rejection Ratio
The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common-mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal VIN(+) voltage which is (VIN(–) + 0.5 LSB)
when operating in the unipolar mode.
Bipolar Offset Error
This is the deviation of the midscale transition (111...11
to 000...00) from the ideal VIN(+) voltage which is (VIN(–)
–0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above minus full scale. The last code transition should
occur for an analog value 3/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
Signal-to-(Noise + Distortion)
Signal-to-(Noise + Distortion) is measured signal-to-noise at the
output of the ADC. The signal is the rms magnitude of the
fundamental. Noise plus distortion is the rms sum of all of the
nonfundamental signals and harmonics to half the output word
rate (f
MCLK
/128), excluding dc. Signal-to-(Noise + Distortion) is
dependent on the number of quantization levels used in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical Signal-to-(Noise + Distortion) ratio
for a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
where N is the number of bits.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD7720, THD is defined as
THD = 20 log
(V
2
2
+V
3
2
+V
4
2
+V
5
2
+V
6
2
)
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonic.
Spurious Free Dynamic Range
Spurious free dynamic range is the difference, in dB, between
the peak spurious or harmonic component in the ADC output
spectrum (up to f
MCLK
/128 and excluding dc) and the rms value
of the fundamental. Normally, the value of this specification will
be determined by the largest harmonic in the output spectrum
of the FFT. For input signals whose second harmonics occur in
the stop band region of the digital filter, a spur in the noise floor
limits the spurious free dynamic range.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m or n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
(AVDD = DVDD = 5.0 V, T
A
= +258C; CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode; V
IN
(+) = 0 V to 2.5 V, V
IN
(–) = 1.25 V unless otherwise
noted)
AD7720–Typical Characteristics
–8–
REV. 0
INPUT LEVEL – dB
dB
110
100
50
–40 –30 0
–20 –10
90
80
70
60
SFDR
S/ (N+D)
Figure 5. S/(N+D) and SFDR vs.
Analog Input Level
INPUT FREQUENCY – kHz
dB
–85
–90
–115
0 20 100
40 60 80
–95
–100
–105
–110
THD
SNR
SFDR
V
IN
(+) = V
IN
(–) = 1.25Vpk–pk
V
CM
= 2.5V
Figure 8. SNR, THD, and SFDR vs.
Input Frequency
TEMPERATURE – °C
dB
–94
–116
–50 –25 100
0255075
–96
–108
–110
–112
–114
–100
–102
–106
–104
–98
THD
3RD
4TH
2ND
Figure 11. THD vs. Temperature
OUTPUT DATA RATE – kSPS
dB
84
92
85
88
89
90
91
86
87
0 50 300
100 150 200 250
AIN = 1/5 · BW
Figure 6. S/(N+D) vs. Output Sample
Rate
OUTPUT DATA RATE – kSPS
dB
84
92
85
88
89
90
91
86
87
0 50 300
100 150 200 250
AIN = 1/5
·
BW
V
IN
(+) = V
IN
(–) = 1.25Vpk–pk
V
CM
= 2.5V
Figure 9. S/(N+D) vs. Output Sample
Rate
CODES
FREQUENCY OF OCCURENCE
5000
0
n–3 n–2 n+3
n–1 n n+1 n+2
4500
2000
1500
1000
500
4000
3500
2500
3000
V
IN
(+) = V
IN
(–)
CLKIN = 12.5MHz
8k SAMPLES
Figure 12. Histogram of Output Codes
with DC Input
INPUT FREQUENCY – kHz
dB
–85
–90
–115
0 20 100
40 60 80
–95
–100
–105
–110
SNR
SFDR
THD
Figure 7. SNR, THD, and SFDR vs.
Input Frequency
TEMPERATURE – °C
92.0
91.5
88.0
–50 0 100
50
90.0
89.5
88.5
89.0
91.0
90.5
dB
Figure 10. SNR vs. Temperature
CODE
DNL ERROR – LSB
1.0
0.8
–1.0
0 20000 6553540000
–0.4
–0.8
–0.6
0
–0.2
0.6
0.2
0.4
Figure 13. Differential Nonlinearity

AD7720BRUZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS Modulator w/ 90dB Dynamic Range
Lifecycle:
New from this manufacturer.
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