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PHD37N06LT,118

P1-P3P4-P6P7-P9P10-P10
Philips Semiconductors Product specification
TrenchMOS transistor PHP37N06LT, PHB37N06LT, PHD37N06LT
Logic level FET
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology V
DSS
= 55 V
• Very low on-state resistance
• Fast switching I
D
= 37 A
• Stable off-state characteristics
• High thermal cycling performance R
DS(ON)
≤ 35 mΩ (V
GS
= 5 V)
• Low thermal resistance
R
DS(ON)
≤ 32 mΩ (V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP37N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB37N06LT is supplied in the SOT404 surface mounting package.
The PHD37N06LT is supplied in the SOT428 surface mounting package.
PINNING SOT78 (TO220AB) SOT404 SOT428
PIN DESCRIPTION
1 gate
2 drain
1
3 source
tab drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DSS
Drain-source voltage T
j
= 25 ˚C to 175˚C - 55 V
V
DGR
Drain-gate voltage T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ -55V
V
GS
Gate-source voltage - ± 13 V
I
D
Continuous drain current T
mb
= 25 ˚C - 37 A
T
mb
= 100 ˚C - 26 A
I
DM
Pulsed drain current T
mb
= 25 ˚C - 148 A
P
D
Total power dissipation T
mb
= 25 ˚C - 100 W
T
j
, T
stg
Operating junction and - 55 175 ˚C
storage temperature
d
g
s
1
2
3
tab
13
tab
2
123
tab
1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
September 1998 1 Rev 1.400
Philips Semiconductors Product specification
TrenchMOS transistor PHP37N06LT, PHB37N06LT, PHD37N06LT
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction - 1.5 K/W
to mounting base
R
th j-a
Thermal resistance junction SOT78 package, in free air 60 - K/W
to ambient SOT404 and SOT428 packages, pcb 50 - K/W
mounted, minimum footprint
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
C
Electrostatic discharge Human body model (100 pF, 1.5 kΩ)-2kV
capacitor voltage, all pins
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown V
GS
= 0 V; I
D
= 0.25 mA; 55 - - V
voltage T
j
= -55˚C 50 - - V
V
(BR)GSS
Gate-source breakdown I
G
= ±1 mA; 10 - - V
voltage
V
GS(TO)
Gate threshold voltage V
DS
= V
GS
; I
D
= 1 mA 1.0 1.5 2.0 V
T
j
= 175˚C 0.5 - - V
T
j
= -55˚C - - 2.3 V
R
DS(ON)
Drain-source on-state V
GS
= 5 V; I
D
= 17 A - 28 35 mΩ
resistance V
GS
= 10 V; I
D
= 17 A - 26 32 mΩ
T
j
= 175˚C - - 74 mΩ
g
fs
Forward transconductance V
DS
= 25 V; I
D
= 15 A 12 40 - S
I
GSS
Gate source leakage current V
GS
= ±5 V; V
DS
= 0 V - 0.02 1 µA
T
j
= 175˚C - - 20 µA
I
DSS
Zero gate voltage drain V
DS
= 55 V; V
GS
= 0 V; - 0.05 10 µA
current T
j
= 175˚C - - 500 µA
Q
g(tot)
Total gate charge I
D
= 30 A; V
DD
= 44 V; V
GS
= 5 V - 22.5 - nC
Q
gs
Gate-source charge - 6 - nC
Q
gd
Gate-drain (Miller) charge - 11 - nC
t
d on
Turn-on delay time V
DD
= 30 V; I
D
= 25 A; - 14 21 ns
t
r
Turn-on rise time V
GS
= 5 V; R
G
= 10 Ω - 77 110 ns
t
d off
Turn-off delay time Resistive load - 55 80 ns
t
f
Turn-off fall time - 48 65 ns
L
d
Internal drain inductance Measured from tab to centre of die - 3.5 - nH
L
d
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
(SOT78 package only)
L
s
Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
C
iss
Input capacitance V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz - 1050 1400 pF
C
oss
Output capacitance - 205 245 pF
C
rss
Feedback capacitance - 113 150 pF
September 1998 2 Rev 1.400
Philips Semiconductors Product specification
TrenchMOS transistor PHP37N06LT, PHB37N06LT, PHD37N06LT
Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
S
Continuous source current - - 37 A
(body diode)
I
SM
Pulsed source current (body - - 148 A
diode)
V
SD
Diode forward voltage I
F
= 25 A; V
GS
= 0 V - 0.95 1.2 V
I
F
= 34 A; V
GS
= 0 V - 1.0 - V
t
rr
Reverse recovery time I
F
= 34 A; -dI
F
/dt = 100 A/µs; - 40 - ns
Q
rr
Reverse recovery charge V
GS
= -10 V; V
R
= 30 V - 0.16 - µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
W
DSS
Drain-source non-repetitive I
D
= 20 A; V
DD
≤ 25 V; V
GS
= 5 V; - 45 mJ
unclamped inductive turn-off R
GS
= 50 Ω; T
mb
= 25 ˚C
energy
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
0 20 40 60 80 100 120 140 160 180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
September 1998 3 Rev 1.400
P1-P3P4-P6P7-P9P10-P10

PHD37N06LT,118

Mfr. #:
Buy PHD37N06LT,118
Manufacturer:
NXP Semiconductors
Description:
MOSFET N-CH 55V 37A DPAK
Lifecycle:
New from this manufacturer.
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