© Semiconductor Components Industries, LLC, 2017
January, 2017 − Rev. 9
1 Publication Order Number:
NB3L553/D
NB3L553
2.5 V / 3.3 V / 5.0 V
1:4 Clock Fanout Buffer
Description
The NB3L553 is a low skew 1−to 4 clock fanout buffer, designed for
clock distribution in mind. The NB3L553 specifically guarantees low
output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
Features
• Input/Output Clock Frequency up to 200 MHz
• Low Skew Outputs (35 ps), Typical
• RMS Phase Jitter (12 kHz – 20 MHz): 29 fs (Typical)
• Output goes to Three−State Mode via OE
• Operating Range: V
DD
= 2.375 V to 5.25 V
• 5 V Tolerant Input Clock I
CLK
• Ideal for Networking Clocks
• Packaged in 8−pin SOIC
• Industrial Temperature Range
• These are Pb−Free Devices
Figure 1. Block Diagram
I
CLK
Q1
Q2
Q3
Q4
OE
Device Package Shipping
†
ORDERING INFORMATION
NB3L553DG SOIC−8
(Pb−Free)
98 Units/Rail
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
www.onsemi.com
1
8
3L553 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
3L553
ALYW
G
1
8
NB3L553DR2G SOIC−8
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
I
CLK
Q2
Q3
OE
V
DD
Q0
Q1
GND
PINOUT DIAGRAM
1
DFN8
MN SUFFIX
CASE 506AA
6P = Specific Device Code
M
= Date Code
G = Pb−Free Package
6P MG
G
1
NB3L553MNR4G DFN−8
(Pb−Free)
1000/Tape & Reel
(Note: Microdot may be in either location)
1
2
3
4
8
7
6
5
*For additional marking information, refer to
Application Note AND8002/D.