AT17F16A [DATASHEET]
Atmel-3474F-CNFG-AT17F16A-Datasheet_012015
2
1. Pin Configurations
Table 1-1. Pin Descriptions
Notes: 1. Internal 20K pull-up resistor
2. Internal 30K pull-up resistor
Pin Description
DATA
(1)
Three-state DATA output for FPGA Configuration. Open-collector bi-directional pin for
configuration programming.
DCLK
(1)
Three-state Clock. Functions as an input when the Configurator is in programming mode (i.e.
SER_EN is Low) and as an output during FPGA configuration.
PAGE_EN
(2)
Enable Page Download Mode Input. When PAGE_EN is high the configuration download address
space is partitioned into four equal pages. This gives users the ability to easily store and retrieve
multiple configuration bitstreams from a single configuration device. This input works in conjunction
with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When
SER_EN is
Low (ISP mode) this pin has no effect.
PAGESEL[1:0]
(2)
Page Select Inputs. Used to determine which of the four memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in Table 1-2. When
SER_EN is Low (ISP mode) these pins have no effect.
RESET/OE
(1)
Output Enable (Active High) and RESET (Active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with nCS Low) enables the data
output driver.
nCS
(1)
Chip Enable Input (Active Low). A Low level (with OE High) allows DCLK to increment the address
counter and enables the data output driver. A High level on nCS disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming mode (
SER_EN Low).
GND Ground. A 0.2μF decoupling capacitor between V
CC
and GND is recommended.
nCASC
Cascade Select Output (when SER_EN is High). This output goes Low when the internal address
counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the
highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the four
partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the address
maximum value is the highest address in the device (Table 1-2). In a daisy chain of the AT17FxxxA
Series devices, the nCASC pin of one device must be connected to the nCS input of the next device
in the chain. It will stay Low as long as nCS is Low and OE is High. It will then follow nCS until OE
goes Low; thereafter, nCASC will stay High until the entire EEPROM is read again.
A2
(1)
Device Selection Input, (when SER_EN Low). The input is used to enable (or chip select) the
device during programming (i.e., when
SER_EN is Low). Refer to the Atmel AT17FxxxA
Programming Specification available at www.atmel.com for additional details.
READY
Open Collector Reset State Indicator. Driven Low during power-up reset, released when power-up
is complete. (recommended 4.7k pull-up on this pin if used).
SER_EN
(1)
Serial Enable Input. Must remain High during FPGA configuration operations. Bringing SER_EN
Low enables the 2-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be
tied to V
CC
.
V
CC
Device Power Supply. +3.3V (±10%)
