LTC3851AEMSE-1#TRPBF Datasheet LTC3851AIUD-1#PBF, LTC3851AEUD-1#TRPBF, LTC3851AHMSE-1#PBF | P19-P21

LTC3851A-1

3851a1fa

applicaTions inForMaTion

The required ESR due to a load current step is:

ESR

≤

∆V

∆I

where

∆

I is the change in current from full load to zero load

(or minimum load) and

∆

V is the allowed voltage devia-

tion (not including any droop due to ﬁnite capacitance).

The amount of capacitance needed is determined by the

maximum energy stored in the inductor. The capacitance

must be sufﬁcient to absorb the change in inductor

current when a high current to low current transition

occurs. The opposite load current transition is generally

determined by the control loop OPTI-LOOP components,

so make sure not to over compensate and slow down

the response. The minimum capacitance to assure the

inductors’ energy is adequately absorbed is:

OUT

L ∆I

( )

2 ∆V

( )

OUT

where ∆I is the change in load current.

Manufacturers such as Nichicon, United Chemi-Con and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor electrolyte

capacitor available from Sanyo has the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

In surface mount applications, ESR, RMS current han dling

and load step speciﬁcations may require multiple capaci-

tors in parallel. Aluminum electrolytic, dry tantalum and

special polymer capacitors are available in surface mount

packages. Special polymer surface mount capaci tors offer

very low ESR but have much lower capacitive density per

unit volume than other capacitor types. These capacitors

offer a very cost-effective output capacitor solution and are

an ideal choice when combined with a controller having

high loop bandwidth. Tantalum capaci tors offer the highest

capacitance density and are often used as output capaci-

tors for switching regulators having controlled soft-start.

Several excellent surge-tested choices are the AVX TPS,

AVX TPSV or the KEMET T510 series of surface mount

tantalums, available in case heights rang ing from 1.5mm

to 4.1mm. Aluminum electrolytic capaci tors can be used

in cost-driven applications, provided that consideration is

given to ripple current ratings, tempera ture and long-term

reliability. A typical application will require several to many

aluminum electrolytic capacitors in parallel. A combina-

tion of the above mentioned capaci tors will often result

in maximizing performance and minimizing overall cost.

Other capacitor types include Nichicon PL series, NEC

Neocap, Panasonic SP and Sprague 595D series. Consult

manufacturers for other speciﬁc recommendations.

Like all components, capacitors are not ideal. Each

ca pacitor has its own beneﬁts and limitations. Combina-

tions of different capacitor types have proven to be a very

cost effective solution. Remember also to include high

frequency decoupling capacitors. They should be placed

as close as possible to the power pins of the load. Any

inductance present in the circuit board traces negates

their usefulness.

Setting Output Voltage

The LTC3851A-1 output voltage is set by an external feed-

back resistive divider carefully placed across the output,

as shown in Figure 6. The regulated output volt age is

determined by:

OUT

= 0.8V 1+

⎛

⎝

⎜

⎞

⎠

⎟

To improve the transient response, a feed-forward

ca pacitor, C

, may be used. Great care should be taken

to route the V

line away from noise sources, such as

the inductor or the SW line.

Figure 6. Settling Output Voltage

LTC3851A-1

OUT

3851A1 F06

LTC3851A-1

3851a1fa

applicaTions inForMaTion

Fault Conditions: Current Limit and Current Foldback

The LTC3851A-1 includes current foldback to help limit

load current when the output is shorted to ground. If the

output falls below 40% of its nominal output level, the

maximum sense voltage is progressively lowered from

its maximum programmed value to about 25% of the

that value. Foldback current limiting is disabled during

soft-start or tracking. Under short-circuit conditions

with very low duty cycles, the LTC3851A-1 will begin

cycle skipping in order to limit the short-circuit current.

In this situation the bottom MOSFET will be dissipating

most of the power but less than in normal operation. The

short-circuit ripple current is determined by the minimum

on-time, t

ON(MIN)

, of the LTC3851A-1 (≈90ns), the input

voltage and inductor value:

∆I

L(SC)

= t

ON(MIN)

•

The resulting short-circuit current is:

1/4MaxV

SENSE

–

∆I

L(SC)

Programming Switching Frequency

To set the switching frequency of the LTC3851A-1, connect

a resistor, R

FREQ

, between FREQ/PLLFLTR and GND. The

relationship between the oscillator frequency and R

FREQ

is shown in Figure 7. A 0.1µF bypass capacitor should be

connected in parallel with R

FREQ

Phase-Locked Loop and Frequency Synchronization

The LTC3851A-1 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (V

) and a

phase detector. This allows the turn-on of the top MOSFET

to be locked to the rising edge of an external clock signal

applied to the MODE/PLLIN pin. This phase detector is

an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false lock to

harmonics of the external clock.

The output of the phase detector is a pair of complemen-

tary current sources that charge or discharge the external

ﬁlter network connected to the FREQ/PLLFLTR pin. Note

that the LTC3851A-1 can only be synchronized to an

external clock whose frequency is within range of the

LTC3851A-1’s internal V

.This is guaranteed to be be-

tween 250kHz and 750kHz. A simpliﬁed block diagram is

shown in Figure 8.

If the external clock frequency is greater than the internal

oscillator’s frequency, f

OSC

, then current is sunk con-

tinuously from the phase detector output, pulling down the

FREQ/PLLFLTR pin. When the external clock frequency is

less than f

OSC

, current is sourced continuously, pulling up

the FREQ/PLLFLTR pin. If the external and internal frequen-

cies are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to the

phase difference. The voltage on the FREQ/PLLFLTR pin is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the ﬁlter capacitor C

holds the voltage.

Figure 7. Relationship Between Oscillator Frequency

and Resistor Connected Between FREQ/PLLFLTR and GND

Figure 8. Phase-Locked Loop Block Diagram

FREQ

(kΩ)

250

OSCILLATOR FREQUENCY (kHz)

300

400

450

500

750

600

100

120

3851A1 F07

350

650

700

550

140

160

DIGITAL

PHASE/

FREQUENCY

DETECTOR

VCO

2.7V

3851A1 F08

FREQ/PLLFLTR

EXTERNAL

OSCILLATOR

MODE/

PLLIN

LTC3851A-1

3851a1fa

applicaTions inForMaTion

The loop ﬁlter components, C

and R

, smooth out

the current pulses from the phase detector and provide

a stable input to the voltage-controlled oscillator. The

ﬁlter components C

and R

determine how fast the

loop acquires lock. Typically R

is 1k to 10k and C

2200pF to 0.01μF.

When the external oscillator is active before the LTC3851

is enabled, the internal oscillator frequency will track the

external oscillator frequency as described in the preceding

paragraphs. In situations where the LTC3851 is enabled

before the external oscillator is active, a low free-running

oscillator frequency of approximately 50kHz will result. It is

possible to increase the free-running, pre-synchronization

frequency by adding a second resistor, R

FREQ

, in parallel

with R

and C

. R

FREQ

will also cause a phase difference

between the internal and external oscillator signals. The

magnitude of the phase difference is inversely proportional

to the value R

FREQ

. The free-running frequency may be

programmed by using Figure 7 to determine the appropri-

ate value of R

FREQ

. In order to maintain adequate phase

margin for the PLL, the typical value for C

is 0.01µF and

the typical value for R

is 1k.

The external clock (on MODE/PLLIN pin) input high

threshold is nominally 1.6V, while the input low thres hold

is nominally 1.2V.

Minimum On-Time Considerations

Minimum on-time, t

ON(MIN)

, is the smallest time dura-

tion that the LTC3851A-1 is capable of turning on the top

MOSFET. It is determined by internal timing delays and the

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

ON(MIN)

OUT

(f)

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The minimum on-time for the LTC3851A-1 is approximately

90ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases. This is of particu-

lar concern in forced continuous applications with low

ripple current at light loads. If the duty cycle drops below

the minimum on-time limit in this situation, a signiﬁcant

amount of cycle skipping can occur with correspondingly

larger current and voltage ripple.

Efﬁciency Considerations

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

the losses in LTC3851A-1 circuits: 1) IC V

current, 2)

INTV

regulator current, 3) I

R losses, 4) topside MOSFET

transition losses.

1. The V

current is the DC supply current given in the

Electrical Characteristics table, which excludes MOSFET

driver current. V

current typi cally results in a small

(<0.1%) loss.

INTV

current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

from INTV

to ground. The resulting dQ/dt is a cur rent

out of INTV

that is typically much larger than the

control circuit current. In continuous mode, I

GATECHG

= f(Q

+ Q

), where Q

and Q

are the gate charges of

the topside and bottom side MOSFETs.

3. I

R losses are predicted from the DC resistances of

the fuse (if used), MOSFET, inductor and current sense

resistor. In continuous mode, the average output current

ﬂows through L and R

SENSE

, but is chopped between

the topside MOSFET and the synchronous MOSFET.

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Description:

Switching Voltage Regulators 40Vin Synchronous Step-Down Switching Controller

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