ISPGDX80VA-3T100 Datasheet ISPGDX80VA-5T100, ISPGDX80VA-5T100I, ISPGDX80VA-3T100 | P1-P3

ispGDX

80VA

In-System Programmable

3.3V Generic Digital Crosspoint

Functional Block DiagramFeatures

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL

CROSSPOINT FAMILY

— Advanced Architecture Addresses Programmable

PCB Interconnect, Bus Interface Integration and

Jumper/Switch Replacement

— “Any Input to Any Output” Routing

— Fixed HIGH or LOW Output Option for Jumper/DIP

Switch Emulation

— Space-Saving PQFP and BGA Packaging

— Dedicated IEEE 1149.1-Compliant Boundary Scan

Test

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

— 3.3V Core Power Supply

— 3.0ns Input-to-Output/3.0ns Clock-to-Output Delay

— 250MHz Maximum Clock Frequency

— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels (Individually Programmable)

— Low-Power: 16.5mA Quiescent Icc

— 24mA I

Drive with Programmable Slew Rate

Control Option

— PCI Compatible Drive Capability

— Schmitt Trigger Inputs for Noise Immunity

— Electrically Erasable and Reprogrammable

— Non-Volatile E

CMOS Technology

• ispGDXV OFFERS THE FOLLOWING ADVANTAGES

— 3.3V In-System Programmable Using Boundary Scan

Test Access Port (TAP)

— Change Interconnects in Seconds

• FLEXIBLE ARCHITECTURE

— Combinatorial/Latched/Registered Inputs or Outputs

— Individual I/O Tri-state Control with Polarity Control

— Dedicated Clock/Clock Enable Input Pins (two) or

Programmable Clocks/Clock Enables from I/O Pins (20)

— Single Level 4:1 Dynamic Path Selection (Tpd = 3.0ns)

— Programmable Wide-MUX Cascade Feature

Supports up to 16:1 MUX

— Programmable Pull-ups, Bus Hold Latch and Open

Drain on I/O Pins

— Outputs Tri-state During Power-up (“Live Insertion”

Friendly)

• LEAD-FREE PACKAGE OPTIONS

Global Routing

Pool

(GRP)

I/O

Cells

I/O Pins B

Boundary

Scan

Control

I/O

Cells

ISP

Control

I/O Pins A

I/O Pins C

I/O Pins D

Description

The ispGDXVA architecture provides a family of fast,

flexible programmable devices to address a variety of

system-level digital signal routing and interface require-

ments including:

• Multi-Port Multiprocessor Interfaces

•Wide Data and Address Bus Multiplexing

(e.g. 16:1 High-Speed Bus MUX)

• Programmable Control Signal Routing

(e.g. Interrupts, DMAREQs, etc.)

• Board-Level PCB Signal Routing for Prototyping or

Programmable Bus Interfaces

The devices feature fast operation, with input-to-output

signal delays (Tpd) of 3.0ns and clock-to-output delays of

3.0ns.

The architecture of the devices consists of a series of

programmable I/O cells interconnected by a Global Rout-

ing Pool (GRP). All I/O pin inputs enter the GRP directly

or are registered or latched so they can be routed to the

required I/O outputs. I/O pin inputs are defined as four

sets (A,B,C,D) which have access to the four MUX inputs

gdx80va_05

are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037; http://www.latticesemi.com

Lead-

Free

Package

Options

Available!

Specifications ispGDX80VA

Description (Continued)

found in each I/O cell. Each output has individual, pro-

grammable I/O tri-state control (OE), output latch clock

(CLK), clock enable (CLKEN), and two multiplexer con-

trol (MUX0 and MUX1) inputs. Polarity for these signals

is programmable for each I/O cell. The MUX0 and MUX1

inputs control a fast 4:1 MUX, allowing dynamic selection

of up to four signal sources for a given output. A wider

16:1 MUX can be implemented with the MUX expander

feature of each I/O and a propagation delay increase of

2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs

can be driven directly from selected sets of I/O pins.

Optional dedicated clock input pins give minimum clock-

to-output delays. CLK and CLKEN share the same set of

I/O pins. CLKEN disables the register clock when

CLKEN = 0.

Through in-system programming, connections between

I/O pins and architectural features (latched or registered

inputs or outputs, output enable control, etc.) can be

defined. In keeping with its data path application focus,

the ispGDXVA devices contain no programmable logic

arrays. All input pins include Schmitt trigger buffers for

noise immunity. These connections are programmed

into the device using non-volatile E

CMOS technology.

Non-volatile technology means the device configuration

is saved even when the power is removed from the

device.

In addition, there are no pin-to-pin routing constraints for

1:1 or 1:n signal routing. That is,

any

I/O pin configured

as an input can drive one or more I/O pins configured as

outputs.

The device pins also have the ability to set outputs to

fixed HIGH or LOW logic levels (Jumper or DIP Switch

mode). Device outputs are specified for 24mA sink and

12mA source current (at JEDEC LVTTL levels) and can

be tied together in parallel for greater drive. On the

ispGDXVA, each I/O pin is individually programmable for

3.3V or 2.5V output levels as described later. Program-

mable output slew rate control can be defined

independently for each I/O pin to reduce overall ground

bounce and switching noise.

All I/O pins are equipped with IEEE1149.1-compliant

Boundary Scan Test circuitry for enhanced testability. In

addition, in-system programming is supported through

the Test Access Port via a special set of private com-

mands.

The ispGDXVA I/Os are designed to withstand “live

insertion” system environments. The I/O buffers are

disabled during power-up and power-down cycles. When

designing for “live insertion,” absolute maximum rating

conditions for the Vcc and I/O pins must still be met.

Table 1. ispGDXVA Family Members

ispGDXV/VA Device

ispGDX160V/VA

I/O Pins 160

I/O-OE Inputs* 40

I/O-CLK / CLKEN Inputs* 40

I/O-MUXsel1 Inputs* 40

I/O-MUXsel2 Inputs* 40

BSCAN Interface 4

RESET

Pin Count/Package 208-Pin PQFP

208-Ball fpBGA

272-Ball BGA

* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to

25% of the I/Os.

** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and

CLKEN3 respectively in all devices.

TOE

Dedicated Clock Pins** 4

EPEN 1

100-Pin TQFP

240

388-Ball fpBGA

ispGDX80VA

ispGDX240VA

Specifications ispGDX80VA

Architecture

The ispGDXVA architecture is different from traditional

PLD architectures, in keeping with its unique application

focus. The block diagram is shown below. The program-

mable interconnect consists of a single Global Routing

Pool (GRP). Unlike ispLSI

devices, there are no pro-

grammable logic arrays on the device. Control signals for

OEs, Clocks/Clock Enables and MUX Controls must

come from designated sets of I/O pins. The polarity of

these signals can be independently programmed in each

I/O cell.

Each I/O cell drives a unique pin. The OE control for each

I/O pin is independent and may be driven via the GRP by

one of the designated I/O pins (I/O-OE set). The I/O-OE

set consists of 25% of the total I/O pins. Boundary Scan

test is supported by dedicated registers at each I/O pin.

In-system programming is accomplished through the

standard Boundary Scan protocol.

The various I/O pin sets are also shown in the block

diagram below. The A, B, C, and D I/O pins are grouped

together with one group per side.

I/O Architecture

Each I/O cell contains a 4:1 dynamic MUX controlled by

two select lines as well as a 4x4 crossbar switch con-

trolled by software for increased routing flexiability (Figure

1). The four data inputs to the MUX (called M0, M1, M2,

and M3) come from I/O signals in the GRP and/or

adjacent I/O cells. Each MUX data input can access one

quarter of the total I/Os. For example, in an 80-I/O

ispGDXVA, each data input can connect to one of 20 I/O

pins. MUX0 and MUX1 can be driven by designated I/O

pins called MUXsel1 and MUXsel2. Each MUXsel input

covers 25% of the total I/O pins (e.g. 20 out of 80). MUX0

and MUX1 can be driven from either MUXsel1 or MUXsel2.

Figure 1. ispGDXVA I/O Cell and GRP Detail (80 I/O Device)

I/OCell 0

I/O Cell 1

I/O Cell 38

I/O Cell 39

40 I/O Cells

Boundary

Scan Cell

Bypass Option

I/O Cell N

or Latch

I/O

Prog.

Pull-up

(VCCIO)

Prog. Slew Rate

CLK

Reset

4-to-1 MUX

80 Input GRP

Inputs Vertical

Outputs Horizontal

I/O Cell 79

I/O Cell 78

I/O Cell 41

I/O Group A

I/O Group B

I/O Group C

I/O Group D

4x4

Crossbar

Switch

MUX1MUX0

Global

Reset

I/O Cell 40

• • • • • •

•

40 I/O Cells

ispGDXVA architecture enhancements over ispGDX (5V)

•

CMOS

Programmable

Interconnect

Logic “0”

Logic “1”

80 I/O Inputs

Y0-Y3

Global

Clocks /

Clock_Enables

Prog.

Bus Hold

Latch

CLK_EN

From MUX Outputs

of 2 Adjacent I/O Cells

From MUX Outputs

of 2 Adjacent I/O Cells

To 2 Adjacent

I/O Cells above

To 2 Adjacent

I/O Cells below

Prog. Open Drain

2.5V/3.3V Output

•

N+1

N+2

N-1

N-2

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

ISPGDX80VA-3T100

Mfr. #:

Buy ISPGDX80VA-3T100

Manufacturer:

Lattice

Description:

Analog & Digital Crosspoint ICs 3.3V 80 I/O

Lifecycle:

New from this manufacturer.

Delivery:

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ISPGDX80VA-3T100

ISPGDX80VA-3T100

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