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ISPGDX80VA-9T100I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
10
Specifications ispGDX80VA
DC Electrical Characteristics for 2.5V Range
Over Recommended Operating Conditions
VIH
SYMBOL
2.5V/gdxva
VOH
PARAMETER
Input High Voltage
Output High Voltage
V
OH(MIN)
≤ V
OUT
or V
OUT
≤ V
OL(MAX)
V
OH(MIN)
≤ V
OUT
or V
OUT
≤ V
OL(MAX)
V
CCIO=MIN
,
I
OH
=
-8mA
V
CCIO=MIN
,
I
OL
=
8mA
CONDITION MIN. TYP. MAX. UNITS
1.7
1.8
–
–
5.25
–
V
VCCIO
VIL
I/O Reference Voltage
Input Low Voltage
2.3
-0.3
––
–
2.7
0.7
V
V
V
V
CCIO=MIN
,
I
OH
=
-100µA
2.1 – – V
––0.6 V
V
CCIO=MIN
,
I
OL
=
100µA
––0.2 V
VOL
Output Low Voltage
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
1. One output at a time for a maximum of one second. V
OUT
= 0.5V was selected to avoid test problems by
tester ground degradation. Characterized, but not 100% tested.
2. Typical values are at V
CC
= 3.3V and T
A
= 25°C.
3. I
CC
/ MHz = (0.002 x I/O cell fanout) + 0.022.
e.g. An input driving four I/O cells at 40MHz results in a dynamic I
CC
of approximately ((0.002 x 4) + 0.022) x 40 = 1.20mA.
4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals.
5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.
DC Char_gdx80va
IPU
IBHLS
PARAMETER
I/O Active Pullup Current
Bus Hold Low Sustaining Current
IIH
IIL
Input or I/O High Leakage Current
Input or I/O Low Leakage Current 0V ≤ V
IN
≤ V
IL (MAX)
CONDITION MIN. TYP.
2
MAX. UNITS
–
–
–
–
–
–
–
–
-10
10
-200
50
µA
IBHT
Bus Hold Trip Points
V
IL
–V
IH
V
µA
µA
µA
40 – –
µA
(V
CCIO
-0.2) ≤ V
IN
≤ V
CCIO
V
CCIO
≤ V
IN
≤ 5.25V
0V
≤ V
IN
≤ V
IL (MAX)
IOS
1
Output Short Circuit Current – – -250 mA
V
CC
= 3.3V, V
OUT
= 0.5V, T
A
= 25°C
ICCQ
4
Quiescent Power Supply Current – 12 – mA
V
IL
= 0.5V, V
IH
= V
CC
V
IN
= V
IL (MAX)
IBHHS Bus Hold High Sustaining Current -40 – – µA
V
IN
= V
IH (MIN)
IBHLO Bus Hold Low Overdrive Current – – 550 µA
0V ≤ V
IN
≤ V
CCIO
ICC
Dynamic Power Supply Current
per Input Switching
One input toggling at 50% duty cycle,
outputs open.
– See
Note 3
–
mA/
MHz
ICONT
5
Maximum Continuous I/O Pin Sink
Current Through Any GND Pin
–
––160 mA
IBHHO Bus Hold High Overdrive Current – – -550 µA
0V ≤ V
IN
≤ V
CCIO
11
Specifications ispGDX80VA
5.0
5.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5.0
8.5
6.0
9.5
6.0
6.0
6.0
6.0
–
–
14.0
–
5.0
0.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Data Prop. Delay: Any I/O Pin to Any I/O Pin (4:1 MUX)
Data Prop. Delay: MUXsel Inputs to Any Output (4:1 MUX)
Clk. Frequency, Max. Toggle
Clk. Frequency with External Feedback
Input Latch or Reg. Setup Time Before Y
x
Input Latch or Reg. Setup Time Before I/O Clk.
Output Latch or Reg. Setup Time Before Y
x
Output Latch or Reg. Setup Time Before I/O Clk.
Global Clk. Enable Setup Time Before Y
x
Global Clk. Enable Setup Time Before I/O Clk.
I/O Clk. Enable Setup Time Before Y
x
Input Latch or Reg. Hold Time (Y
x
)
Input Latch or Reg. Hold Time (I/O Clk.)
Output Latch or Reg. Hold Time (Y
x
)
Output Latch or Reg. Hold Time (I/O Clk.)
Global Clk. Enable Hold Time (Y
x
)
Global Clk. Enable Hold Time (I/O Clk.)
I/O Clk. Enable Hold Time (Y
x
)
Output Latch or Reg. Clk. (from Y
x
) to Output Delay
Input Latch or Register Clk. (from Y
x
) to Output Delay
Output Latch or Reg. Clk. (from I/O pin) to Output Delay
Input Latch or Reg. Clk. (from I/O pin) to Output Delay
Input to Output Enable
Input to Output Disable
Test OE Output Enable
Test OE Output Disable
Clock Pulse Duration, High
Clock Pulse Duration, Low
Register Reset Delay from RESET Low
Reset Pulse Width
Output Delay Adder for Output Timings Using Slow Slew Rate
Output Skew (tgco1 Across Chip)
External Timing Parameters
Over Recommended Operating Conditions
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
143
111
4.0
3.0
4.0
3.0
2.5
1.5
4.5
0.0
1.5
0.0
1.5
0.0
1.5
0.0
–
–
–
–
–
–
–
–
3.5
3.5
–
10.0
–
–
A
A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A
A
A
A
B
C
B
C
–
–
–
–
D
A
tpd
2
tsel
2
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
tgco1
2
tgco2
2
tco1
2
tco2
2
ten
2
tdis
2
ttoeen
2
ttoedis
2
twh
twl
trst
trw
tsl
tsk
DESCRIPTION
PARAMETER
( )
1
tsu3+tgco1
UNITS
-5
MIN.
MAX.
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
3. The new “-3” speed grade (tpd = 3.0ns) will be effective starting with date code A113xxxx. Devices with topside date codes
prior to A113xxxx adhere to the shaded “-3” speed grade (tpd = 3.5ns).
#
3.0
3.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.0
5.5
3.5
6.0
4.0
4.0
5.5
5.5
–
–
7.0
–
3.0
0.5
–
–
250
208.3
2.2
1.8
1.8
1.5
1.8
1.5
2.5
0.0
0.5
0.0
0.5
0.0
1.0
0.0
–
–
–
–
–
–
–
–
2.0
2.0
–
4.5
–
–
-3
3
MIN.
MAX.
TEST
1
COND.
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.5
6.0
4.0
7.0
5.0
5.0
6.0
6.0
–
–
8.0
–
3.5
0.5
–
–
250
166.7
3.0
2.5
2.5
2.0
2.5
1.5
3.0
0.0
0.5
0.0
1.0
0.0
1.0
0.0
–
–
–
–
–
–
–
–
2.0
2.0
–
5.0
–
–
-3
MIN.
MAX.
12
Specifications ispGDX80VA
9.0
9.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
9.0
13.5
11.5
15.7
10.5
10.5
10.5
10.5
–
–
22.0
–
9.0
1.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Data Prop. Delay: Any I/O pin to Any I/O Pin (4:1 MUX)
Data Prop. Delay: MUXsel Inputs to Any Output (4:1 MUX)
Clk. Frequency, Max. Toggle
Clk. Frequency with External Feedback
Input Latch or Reg. Setup Time Before Y
x
Input Latch or Reg. Setup Time Before I/O Clock
Output Latch or Reg. Setup Time Before Y
x
Output Latch or Reg. Setup Time Before I/O Clk.
Global Clk. Enable Setup Time Before Y
x
Global Clk. Enable Setup Time Before I/O Clk.
I/O Clk. Enable Setup Time Before Y
x
Input Latch or Reg. Hold Time (Y
x
)
Input Latch or Reg. Hold Time (I/O Clk.)
Output Latch or Reg. Hold Time (Y
x
)
Output Latch or Reg. Hold Time (I/O Clk.)
Global Clk. Enable Hold Time (Y
x
)
Global Clk. Enable Hold Time (I/O Clk.)
I/O Clk. Enable Hold Time (Y
x
)
Output Latch or Reg. Clk. (from Y
x
) to Output Delay
Input Latch or Reg. Clk. (from Y
x
) to Output Delay
Output Latch or Reg. Clk. (from I/O pin) to Output Delay
Input Latch or Reg. Clock (from I/O pin) to Output Delay
Input to Output Enable
Input to Output Disable
Test OE Output Enable
Test OE Output Disable
Clk. Pulse Duration, High
Clk. Pulse Duration, Low
Reg. Reset Delay from RESET Low
Reset Pulse Width
Output Delay Adder for Output Timings Using Slow Slew Rate
Output Skew (tgco1 Across Chip)
External Timing Parameters
Over Recommended Operating Conditions
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
83
62.5
7.0
6.0
7.0
6.0
4.0
3.0
8.5
0.0
3.0
0.0
3.0
0.0
3.0
0.0
–
–
–
–
–
–
–
–
6.0
6.0
–
18.0
–
–
A
A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A
A
A
A
B
C
B
C
–
–
–
–
D
A
tpd
2
tsel
2
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
tgco1
2
tgco2
2
tco1
2
tco2
2
ten
2
tdis
2
ttoeen
2
ttoedis
2
twh
twl
trst
trw
tsl
tsk
DESCRIPTION
PARAMETER
( )
1
tsu3+tgco1
UNITS
-9
MIN.
MAX.
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
#
-7
MIN.
MAX.
TEST
1
COND.
–
–
100
80
5.5
4.5
5.5
4.5
3.5
2.5
6.5
0.0
2.5
0.0
2.5
0.0
2.5
0.0
–
–
–
–
–
–
–
–
5.0
5.0
–
14.0
–
–
7.0
7.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
7.0
11.0
9.0
13.0
8.5
8.5
8.5
8.5
–
–
18.0
–
7.0
0.5
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ISPGDX80VA-9T100I

Mfr. #:
Buy ISPGDX80VA-9T100I
Manufacturer:
Lattice
Description:
Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
Lifecycle:
New from this manufacturer.
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