A5957GESTR-T Datasheet A5957GESTR-T | P1-P3

Designed for pulse-width-modulated (PWM) control of DC

motors, the A5957 is capable of 50 V operation and provides

gate drive for an all N-channel external MOSFET bridge.

Input terminals are provided for use in controlling the speed and

direction of a DC motor with externally applied PWM control

signals. Internal synchronous rectification control circuitry is

provided to lower power dissipation during PWM operation.

Internal circuit protection includes VDS protection, thermal

shutdown with hysteresis, undervoltage monitoring of VBB,

and crossover-current protection.

The A5957 is supplied in a low-profile, 4 × 4 mm, 20-contact

QFN package (suffix “ES”) with exposed thermal pad.

A5957-DS, Rev. 2

MCO-0000349

• PHASE/ENABLE/SLEEPn control logic

• Overcurrent indication

• Adjustable off-time and blank-time

• Adjustable current limit

• Adjustable gate drive

• Synchronous rectification

• Internal UVLO

• Crossover-current protection

• MOSFET VDS protection

• Voltage output proportional to load current

Full-Bridge PWM Gate Driver

PACKAGE:

Functional Block Diagram

Not to scale

A5957

CHARGE PUMP

VREG

UVLOTSD

ISET

SLEEPn

PHASE

ENABLE

STANDBY

Control

Logic

VCP

GATE

DRIVE

VCP

VBB

GHA

GHB

CP1

CP2

OCLn

AIOUT

VREF

×10

÷10

OCL

Filter

–

GLA

GLB

SENSE

GND

System

Controller

optional

0.1 µF

VIN

GHA

GLA

SENSE

Inrush current limit =

V/10 * R

REF SENSE

HOLD

FEATURES AND BENEFITS DESCRIPTION

20-Pin QFN (suffix “ES”)

with Exposed Thermal Pad

November 30, 2017

Full-Bridge PWM Gate Driver

A5957

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Unit

Load Supply Voltage V

50 V

Motor Outputs V

– V

SENSE

; V

– V

–2 to 52 V

SENSE V

SENSE

–0.5 to 0.5 V

< 500 ns –4 to 4 V

OCLn V

OCLn

–0.3 to 5.5 V

VREF V

REF

–0.3 to 5.5 V

ISET V

ISET

–0.3 to 5.5 V

AIOUT V

AIOUT

–0.3 to 5.5 V

Logic Input Voltage Range V

PHASE, ENABLE, MODE –0.3 to 5.5 V

Junction Temperature T

150 °C

Storage Temperature Range T

–55 to 150 °C

Operating Temperature Range T

Range G –40 to 105 °C

SELECTION GUIDE

Part Number Ambient Temperature Range Packing

A5957GESTR-T –40°C to 105°C 1500 pieces per 7-inch reel

THERMAL CHARACTERISTICS (may require derating at maximum conditions; see application information)

Characteristic Symbol Test Conditions* Value Unit

ES Package R

θJA

4-Layer PCB, 1 in.

copper 37 °C/W

*Power dissipation and thermal limits must be observed.

SPECIFICATIONS

Full-Bridge PWM Gate Driver

A5957

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Terminal List Table

Name Number Function

ISET 1

Terminal to set gate drive current

SLEEPn 2 Sleep input, active low

SENSE 3 Sense resistor connection, low-side gate return

GLB 4 Gate driver

GLA 5 Gate driver

GHB 6 Gate driver

SB 7 High-side bridge reference

GHA 8 Gate driver

SA 9 High-side bridge reference

VCP 10 Charge pump reservoir cap connection

CP2 11 Charge pump terminal

VBB 12 Supply voltage

CP1 13 Charge pump terminal

GND 14 Ground

AIOUT 15 Analog output proportional to V

SENSE

OCLn 16 OCP and OVP output flag, open drain

VREF 17 Analog OCP reference input

ENABLE 18 Digital ENABLE input

PHASE 19 Digital PHASE input

RC 20 Terminal to set blank- and off-time

PAD –

ISET

SLEEPn

SENSE

GLB

GLA

GHB

GHA

VCP

CP2

VBB

CP1

GND

PAD

AIOUT

OCLn

VREF

ENABLE

PHASE

Package ES, 20-Pin QFN Pinouts

P1-P3 P4-P6 P7-P9 P10-P10

A5957GESTR-T

Mfr. #:

Buy A5957GESTR-T

Manufacturer:

Description:

IC MOTOR DRIVER 5.5V-50V 20QFN

Lifecycle:

New from this manufacturer.

Delivery:

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A5957GESTR-T