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74HC564N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
1. General description
The 74HC564 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC564 is specified in compliance with JEDEC
standard no. 7A.
The 74HC564 is a octal D-type flip-flop featuring separate D-type inputs for each flip-flop
and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output
enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold
times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of
the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
flip-flops.
The 74HC564 is functionally identical to the 74HC574 but has inverting outputs. The
74HC564 is functionally identical to the 74HC534, but has a different pinning.
2. Features
■ 3-state inverting outputs for bus oriented applications
■ 8-bit positive-edge triggered register
■ Common 3-state output enable input
■ Independent register and 3-state buffer operation
■ Low-power dissipation
■ Complies with JEDEC standard no. 7A
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Multiple package options
■ Specified from −40 °Cto+80°C and from −40 °C to +125 °C.
74HC564
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Rev. 03 — 11 November 2004 Product data sheet
9397 750 13814 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 11 November 2004 2 of 18
Philips Semiconductors
74HC564
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
3. Quick reference data
[1] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+∑(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
× V
CC
2
× f
o
) = sum of outputs.
4. Ordering information
Table 1: Quick reference data
GND = 0 V; T
amb
=25
°
C; t
r
=t
f
= 6 ns.
Symbol Parameter Conditions Min Typ Max Unit
t
PHL
, t
PLH
propagation delay CP
to
Qn
C
L
= 15 pF;
V
CC
=5 V
-15 -ns
f
max
maximum clock
frequency
C
L
= 15 pF;
V
CC
=5 V
- 127 - MHz
C
I
input capacitance - 3.5 - pF
C
PD
power dissipation
capacitance per
flip-flop
V
I
= GND to V
CC
[1]
-27 -pF
Table 2: Ordering information
Type number Package
Temperature range Name Description Version
74HC564N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HC564D −40 °C to +125 °C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
9397 750 13814 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 11 November 2004 3 of 18
Philips Semiconductors
74HC564
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
5. Functional diagram
Fig 1. Functional diagram
Fig 2. Logic symbol Fig 3. IEC logic symbol
001aab936
Q0
Q1
Q2
3 STATE
OUTPUTS
FF1 TO
FF8
Q3
Q4
Q5
Q6
Q7
12
13
14
15
16
17
18
19
D0
D1
CP
OE
D2
4
11
1
3
D3
D4
6
5
D5
D6
8
7
D7
9
2
001aab934
D0
D1
D2
D3
D4
D5
D6
D7
CP
OE
11
1
Q0
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aab935
11
1
EN
1D
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
C1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

74HC564N,652

Mfr. #:
Buy 74HC564N,652
Manufacturer:
NXP Semiconductors
Description:
Flip Flops OCTAL D-TYPE 3-S
Lifecycle:
New from this manufacturer.
Delivery:
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