REV. A
–3–
AD7243
Limit at +25C, T
MIN
, T
MAX
Parameter (All Versions) Units Conditions/Comments
t
1
3
200 ns min SCLK Cycle Time
t
2
15 ns min SYNC to SCLK Falling Edge Setup Time
t
3
70 ns min SYNC to SCLK Hold Time
t
4
0 ns min Data Setup Time
t
5
40 ns min Data Hold Time
t
6
0 ns min SYNC High to LDAC Low
t
7
20 ns min LDAC Pulsewidth
t
8
0 ns min LDAC High to SYNC Low
t
9
20 ns min CLR Pulsewidth
t
10
4, 5
160 ns max SCLK Falling Edge to SDO Valid
t
11
4, 6
>t
5
ns min SCLK Falling Edge to SDO Invalid
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 7 & 8.
3
SCLK mark/space ratio range is 40/60 to 60/40.
4
SDO load capacitance is no greater than 50 pF.
5
At 25°C t
10
is 130 ns max.
6
Guaranteed by design.
ORDERING GUIDE
Model Temperature Range Relative Accuracy Package Option
1
AD7243AN –40°C to +85°C ± 1 LSB N-16
AD7243BN –40°C to +85°C ± 1/2 LSB N-16
AD7243AR –40°C to +85°C ± 1 LSB R-16
AD7243BR –40°C to +85°C ± 1/2 LSB R-16
AD7243AQ –40°C to +85°C ± 1 LSB Q-16
AD7243BQ –40°C to +85°C ± 1/2 LSB Q-16
AD7243SQ
2
–55°C to +125°C ± 1 LSB Q-16
NOTES
1
N = Plastic DIP; R = SOIC; Q = Cerdip.
2
Available to /883B processing only. Contact your local sales office for military data sheet.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND, DGND . . . . . . . . . . . . . . . . . –0.3 V to +17 V
V
SS
to AGND, DGND . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
2
to AGND . . . . . . . . . . . . . . . . . . . –6 V to V
DD
+ 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
DD
REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
SDO to DGND . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
TIMING CHARACTERISTICS
1, 2
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any time.
2
The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded. Short circuit current is typically 80 mA.
(V
DD
= +10.8 V to +16.5 V, V
SS
= 0 V or –10.8 V to –16.5 V, AGND = DGND = 0 V,
R
L
= 2 k, C
L
= 100 pF. All Specifications T
MIN
to T
MAX
unless otherwise noted.)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7243 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD7243
–4–
REV. A
AD7243 PIN FUNCTION DESCRIPTIONS (DIP and SOIC PIN NUMBERS)
Pin Mnemonic Description
1 REFIN Voltage Reference Input. It is internally buffered before being applied to the DAC. The nominal reference
voltage for specified operation of the AD7243 is 5 V.
2 REFOUT Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part -
using its internal reference, REFOUT should be connected to REFIN.
3 CLR Clear, Logic Input. Taking this input low sets V
OUT
to 0 V in both unipolar ranges and the two’s complement
bipolar range and to –REFIN in the offset binary bipolar range.
4 BIN/COMP Logic Input. This input selects the data format to be either binary or two’s complement. In both unipolar
ranges, natural binary format is selected by connecting this input to a Logic “0.” In the bipolar configuration,
offset binary format is selected with a Logic “0” while a Logic “1” selects two’s complement format.
5 SCLK Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
6 SDIN Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
7 SYNC Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readiness for a
new data word.
8 DGND Digital Ground. Ground reference for all digital circuitry.
9 LDAC Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of this
signal or alternatively if this line is permanently low, an automatic update mode is selected whereby the DAC
is updated on the 16th falling SCLK pulse.
10 DCEN Daisy-Chain Enable, Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise
this pin must be connected low.
11 SDO Serial Data Out, Logic Output. With DCEN at Logic “1” this output is enabled, and the serial data in the
input shift register is clocked out on each falling SCLK edge.
12 AGND Analog Ground. Ground reference for all analog circuitry.
13 R
OFS
Output Offset Resistor for the amplifier. It is connected to V
OUT
for the +5 V range, to AGND for the +10 V
range and to REFIN for the –5 V to +5 V range.
14 V
OUT
Analog Output Voltage. This is the buffer amplifier output voltage. Three different output voltage ranges can
be chosen: 0 V to +5 V, 0 to +10 V and –5 V to +5 V.
15 V
SS
Negative Power Supply (used for the output amplifier only, may be connected to 0 V for single supply
operation or to –12 V to –15 V for dual supplies).
16 V
DD
Positive Power Supply (+12 V to +15 V).
TERMINOLOGY
Bipolar Zero Error
Bipolar Zero Error is the voltage measured at V
OUT
when the
DAC is configured for bipolar output and loaded with all 0s
(Two’s Complement Coding) or with 1000 0000 0000 (Offset
Binary Coding). It is due to a combination of offset errors in the
DAC, amplifier and mismatch between the internal gain resis-
tors around the amplifier.
Full-Scale Error
Full-Scale Error is a measure of the output error when the am-
plifier output is at full scale (for the bipolar output range full
scale is either positive or negative full scale). It is measured with
respect to the reference input voltage and includes the offset
errors.
Digital-to-Analog Glitch Impulse
This is the voltage spike that appears at V
OUT
when the digital
code in the DAC latch changes, before the output settles to its
final value. The energy in the glitch is specified in nV secs, and
is measured for an all codes change from 0000 0000 0000 to
1111 1111 1111 and vice versa.
Digital Feedthrough
This is a measure of the voltage spike that appears on V
OUT
as a
result of feedthrough from the digital inputs on the AD7243. It
is measured with LDAC held high.
Relative Accuracy (Linearity)
Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer func-
tion. It is measured after allowing for zero and full-scale errors
and is expressed in LSBs or as a percentage of full-scale reading.
Single Supply Linearity and Gain Error
The output amplifier on the AD7243 can have true negative off-
sets even when the part is operated from a single +15 V supply.
However, because the negative supply rail (V
SS
) is 0 V, the out-
put cannot actually go negative. Instead, when the output offset
voltage is negative, the output voltage sits at 0 V, resulting in the
transfer function shown in Figure 1.
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
DAC CODE
0V
{
Figure 1. Effect of Negative Offset (Single Supply)
REV. A
–5–
AD7243
TERMINOLOGY (Continued)
This “knee” is an offset effect, not a linearity error, and the
transfer function would have followed the dotted line if the out-
put voltage could have gone negative.
Normally, linearity is measured between zero (all 0s input code)
and full scale (all 1s input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in
single supply operation if the offset is negative, due to the knee
in the transfer function. Instead, linearity of the AD7243 in the
unipolar mode is measured between full scale and the lowest
code which is guaranteed to produce a positive output voltage.
This code is calculated from the maximum specification for
negative offset. For the A and B versions the linearity is mea-
sured between Codes 3 and 4095. For the S grade, linearity is
measured between Code 5 and Code 4095.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB or less
over the operating temperature range ensures monotonicity.
Unipolar Offset Error
Unipolar Offset Error is the measured output voltage from
V
OUT
with all zeros loaded into the DAC latch when the DAC is
configured for unipolar output. It is due to a combination of the
offset errors in the DAC and output amplifier.
PIN CONFIGURATION
DIP and SOIC
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
REFIN
REFOUT
CLR
BIN/COMP
SCLK
SDIN
SYNC
DGND
AGND
SDO
DCEN
LDAC
V
DD
V
SS
V
OUT
R
OFS
AD7243
CIRCUIT INFORMATION
D/A Section
The AD7243 contains a 12-bit voltage mode D/A converter
consisting of highly stable thin film resistors and high speed
NMOS single-pole, double-throw switches. The output voltage
from the converter has the same polarity as the reference volt-
age, REFIN, allowing single supply operation.
SHOWN FOR ALL 1S
ON DAC
*BUFFERED REFIN VOLTAGE
2R
2R
RR
R
R
R
2R
2R
2R 2R 2R
2R
DB0
DB1
DB9 DB10 DB11
REFIN*
AGND
R
OFS
V
OUT
Figure 2. D/A Simplified Circuit Diagram
Internal Reference
The AD7243 has an on-chip temperature compensated buried
Zener reference which is factory trimmed to 5 V ± 50 mV. The
reference voltage is provided at the REFOUT pin. This refer-
ence can be used to provide the reference voltage for the D/A
converter (by connecting the REFOUT pin to the REFIN pin.)
The reference voltage can also be used as a reference for other
components and is capable of providing up to 500 µA to an ex-
ternal load. The maximum recommended capacitance on
REFOUT for normal operation is 50 pF. If the reference is re-
quired for external use with capacitive loads greater than 50 pF
then it should be decoupled to AGND with a 200 resistor in
series with a parallel combination of a 10 µF tantalum capacitor
and a 0.1 µF ceramic capacitor.
200
10F
0.1F
REFOUT
EXT
LOAD
Figure 3. Reference Decoupling Scheme
External Reference
In some applications, the user may require a system reference or
some other external reference to drive the AD7243. References
such as the AD586 provide an ideal external reference source
(see Figure 10). The REFIN voltage is internally buffered by a
unity gain amplifier before being applied to the D/A converter.
The D/A converter is scaled for a 5 V reference and the device is
tested with 5 V applied to REFIN. Other reference voltages may
be used with degraded performance. Figure 4 shows the typical
degradation in linearity vs. REFIN.
REFIN – Volts
1.0
2
LINEARITY ERROR – LSBs
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
34567 89
V
DD
= +15V
V
SS
= –15V
T
A
= +25C
INL
DNL
Figure 4. Typical Linearity vs. REFIN Voltage
Op Amp Section
The output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The R
OFS
input allows three out-
put voltage ranges to be selected. The buffer amplifier is capable
of developing +10 V across a 2 k load to AGND.
The output amplifier can be operated from a single +12 V to
+15 V supply by tying V
SS
= 0 V.
The amplifier can also be operated from dual supplies to allow
an additional bipolar output range of –5 V to +5 V. Dual supplies are
necessary for the bipolar output range but can also be used for
the unipolar ranges to give faster settling time to voltages near

AD7243ARZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC CMOS 12B SERIAL IC
Lifecycle:
New from this manufacturer.
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