Integrated Silicon Solution, Inc. - www.issi.com 1
Rev. A
04/08/2011
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-
plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS42VM81600E / IS42VM16800E / IS42VM32400E
IS45VM81600E / IS45VM16800E / IS45VM32400E
16Mx8, 8Mx16, 4Mx32
128Mb Mobile Synchronous DRAM
JUNE 2011
FEATURES
Fully synchronous; all signals referenced to a
positive clock edge
Internal bank for hiding row access and pre-
charge
Programmable CAS latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8, and Full
Page
Programmable Burst Sequence:
Sequential and Interleave
Auto Refresh (CBR)
TCSR (Temperature Compensated Self Refresh)
PASR (Partial Arrays Self Refresh): 1/16, 1/8,
1/4, 1/2, and Full
Deep Power Down Mode (DPD)
Driver Strength Control (DS): 1/4, 1/2, and Full
OPTIONS
Configurations: 16M x 8, 8M x 16, 4M x 32
Power Supply
IS42VMxxx – V
dd/Vddq = 1.8 V
Packages:
x8 / x16 –TSOP II (54), BGA (54) [x16 only]
x32 – TSOP II (86), BGA (90)
Temperature Range:
Commercial (0°C to +70°C)
Industrial (–40 ºC to 85 ºC)
Automotive, A1 (–40 ºC to 85 ºC)
Automotive, A2 (–40 ºC to 105 ºC)
Parameter 16M x 8 8M x 16 4M x 32
Configuration 4M x 8 x 4 banks 2M x 16 x 4 banks 1M x 32 x 4 banks
Refresh Count 4K/64ms 4K/64ms 4K/64ms
Row Addressing A0-A11 A0-A11 A0-A11
Column Addressing A0-A9 A0-A8 A0-A7
Bank Addressing BA0, BA1 BA0, BA1 BA0, BA1
Precharge Addressing A10 A10 A10
ADDRESSING TABLE
DESCRIPTION
ISSI's 128Mb Mobile Synchronous DRAM achieves high-
speed data transfer using pipeline architecture. All input
and output signals refer to the rising edge of the clock
input. Both write and read accesses to the SDRAM are
burst oriented. The 128Mb Mobile Synchronous DRAM
is designed to minimize current consumption making it
ideal for low-power applications. Both TSOP and BGA
packages are offered, including industrial grade products.
Parameter -75 -10 Unit
CLK Cycle Time
CAS Latency = 3
7.5 10 ns
CAS Latency = 2
9.6 12 ns
CLK Frequency
CAS Latency = 3
133 100 Mhz
CAS Latency = 2
104 83 Mhz
Access Time from CLK
CAS Latency = 3
5.4 8.0 ns
CAS Latency = 2
8.0 9.0 ns
KEY TIMING PARAMETERS
2 Integrated Silicon Solution, Inc. - www.issi.com
Rev. A
04/08/2011
IS42VM81600E / IS42VM16800E / IS42VM32400E
IS45VM81600E / IS45VM16800E / IS45VM32400E
General Description
ISSI’s 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 1.8V V
DD
/
V
DDQ
memory systems containing 134,271,728 bits. Internally configured as a quad-bank DRAM with a synchronous
interface. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All
signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVCMOS (V
DD
= 1.8V)
compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between internal banks to hide precharge time and the capability to
randomly change column addresses on each clock cycle during burst access.
A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE
function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles
and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented
starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The
registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command
in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 (x8, x16 and x32) select the row). The READ or WRITE commands in conjunction with address bits
registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst
lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.
Functional Block Diagram (8Mx16)
CLK
CKE
CS
RAS
CAS
WE
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
A10
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MULTIPLEXER
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
DATA IN
BUFFER
DATA OUT
BUFFER
DQML
DQMH
DQ 0-15
V
DD/VDDQ
Vss/VssQ
12
12
9
12
12
9
16
16 16
16
512
(x 16)
4096
4096
4096
ROW DECODER
4096
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
ROW
ADDRESS
BUFFER
A11
2
Integrated Silicon Solution, Inc. - www.issi.com 3
Rev. A
04/08/2011
IS42VM81600E / IS42VM16800E / IS42VM32400E
IS45VM81600E / IS45VM16800E / IS45VM32400E
V
DD
DQ0
V
DD
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
DD
Q
NC
DQ3
V
SS
Q
NC
V
DD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
PIN DESCRIPTIONS: 16Mx8
A0-A11 Row Address Input
A0-A9 Column Address Input
BA0, BA1 Bank Select Address
DQ0 to DQ7 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
WE Write Enable
DQM Data Input/Output Mask
Vdd Power
Vss Ground
Vddq Power Supply for I/O Pin
Vssq Ground for I/O Pin
NC No Connection

IS45VM16800E-75BLA1

Mfr. #:
Manufacturer:
Description:
IC DRAM 128M PARALLEL 54TFBGA Automotive, AEC-Q100
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union