ISL29120IROZ-T7 Datasheet ISL29120IROZ-T7 | P4-P6

ISL29120

FN8314.0

May 29, 2012

Principles of Operation

Photodiodes and ADC

The ISL29120 contains three photodiode arrays, which convert

light into current. The spectral response for red, green and blue

color ambient intensity sensing is as shown in Figure 2. After

light is converted to current during the light to signal process, the

current output is converted to a digital count by an on-chip

Analog-to-Digital Converter (ADC). The ADC converter resolution

is selectable from 4, 8, 12 or 16 bits. The ADC conversion time is

inversely proportional to the ADC resolution.

The ADC converter uses an integrating architecture. This

conversion method is ideal for converting small signals in the

presence of a periodic noise. A 100ms integration time (16-bit

mode) for instance, rejects 50Hz and 60Hz power line as well as

florescent flicker noise.

The ADC integration time is determined by an internal oscillator

and the n-bit (n = 4, 8, 12, 16) counter inside the ADC. A good

balancing act of integration time and resolution depends on the

application for optimum system performance.

The ADC provides two programmable ranges to dynamically

accommodate different lighting conditions. For dim conditions,

the ADC can be configured at its high sensitivity (low optical)

range. For bright conditions, the ADC can be configured at its low

sensitivity (higher optical) range.

Note that the effective optical sensitivity of the ISL29120 in

terms of counts/

µW/cm

is directly proportional to the ADC

integration time.

C Interface

There are eight 8-bit registers inside the ISL29120 for

configuration, control and status indication. The two command

registers at address 0x00 and 0x01 define the operation of the

device and provide status of the interrupt events. Two 8-bit read

only registers at address 0x02 and 0x03 are for the ADC output.

These registers contain the results of the latest A/D conversion.

Registers 0x04 and 0x05 contain the ‘low threshold’ value and

registers 0x06 and 0x07 store the ‘high threshold’ value for

interrupt generation.

The ISL29120’s I

C interface slave address is internally hard-wired

as 1000110x, where x is R (read) or W (write) bit.

Figure 4 shows a sample one-byte read. Figure 5 shows a sample

one-byte write. The I

C bus master always drives the SCL (clock)

line, while either the master or the slave can drive the SDA (data)

line. Figure 5 shows a sample write. Every I

C transaction begins

with the master asserting a start condition (SDA falling while SCL

remains high). The following byte is driven by the master, and

includes the slave address and read/write bit. The receiving device

is responsible for pulling SDA low during the acknowledgement

period. Every I

C transaction ends with the master asserting a stop

condition (SDA rising while SCL remains high).

For more information about the I

C standard, consult the

Philips™ I

C specification documents.

FIGURE 4. I

C READ TIMING DIAGRAM SAMPLE

START

A A

A6 A5 A4 A3 A2 A1 A0 W

A R7 R6 R5 R4 R3 R2 R1 R0 A A6 A5 A4 A3 A2 A1 A0 W A

A A AD7D6D5D4D3D2D1D0

1357

123456 9 2 4 6

STOP START

SDA DRIVEN BY MASTER

DEVICE ADDRESS

SDA DRIVEN BY ISL29120

DATA BYTE0REGISTER ADDRESS

OUT

DEVICE ADDRESSI

C DATA

SDA DRIVEN BY MASTER

2468

924689

78135789

C SDA

C CLK

FIGURE 5. I

C WRITE TIMING DIAGRAM SAMPLE

START W A A

A6 A5 A4 A3 A2 A1 A0 W

A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0 A

12615948

STOP

SDA DRIVEN BY MASTER

FUNCTIONSREGISTER ADDRESSDEVICE ADDRESS

SDA DRIVEN BY MASTER

C DATA

C SDA IN

C SDA OUT

C CLK IN

345 789 234 678 123 567 9

ISL29120

FN8314.0

May 29, 2012

There are eight registers that are available in the ISL29120. Table 1 summarizes their functions.

Command Register I 0x00

The first command register has the following functions:

Operation Mode: Bits[7:5]. These three bits determine the

operation mode of the device.

Interrupt flag: Bit[2]. This is the interrupt status bit. The bit is set

high when the interrupt thresholds have been triggered. Once

triggered, the INT

pin stays low and the status bit stays high. Both

the interrupt pin and the status bit are cleared at the end of

Command Register I read.

Interrupt persist: Bits[1:0]. The interrupt pin and the interrupt flag

are triggered/set when the data sensor reading is out of the

interrupt threshold window after m consecutive data conversion

cycles. The interrupt persist bits determine m.

Command Register II 0x01

The second command register has the following functions:

Resolution: Bits[3:2] determine the ADC’s resolution and the

integration time. The integration time is the period the device’s

analog-to-digital (A/D) converter samples the photodiode current

for a measurement.

1. Range 0x01[0]: The Full Scale Optical Range (FSOR). Optical

sensitivity for the ‘Low’ range is 4.75 times the optical

sensitivity in ‘High’ range.

TABLE 1. REGISTER SET

ADDR REG NAME

BIT

765 4 3210DEFAULT

00h COMMANDI OP2 OP1 OP0 0 0 IFLG PRST1 PRST0 00h

01h COMMANDII 0 0 0 0 RES1 RES0 0 RANGE 00h

02h DATA

LSB

D7 D6 D5 D4 D3 D2 D1 D0 00h

03h DATA

MSB

D15 D14 D13 D12 D11 D10 D9 D8 00h

04h INT_LT_LSB TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0 00h

05h INT_LT_MSB TL15 TL14 TL13 TL12 TL11 TL10 TL9 TL8 00h

06h INT_HT_LSB TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0 FFh

07h INT_HT_MSB TH15 TH14 TH13 TH12 TH11 TH10 TH9 TH8 FFh

TABLE 2. OPERATION MODE

0x00[7:5] OPERATION

000 Power-down

001 Red Sensor once

010 Blue Sensor once

011 Green Sensor once

100 Reserved

101 Red Sensor continuous

110 Blue Sensor continuous

111 Green Sensor continuous

TABLE 3. INTERRUPT FLAG

0x00[2] OPERATION

0 No Interrupt event

1 Interrupt event triggered

TABLE 4. INTERRUPT PERSISTENCE

0x00[1:0] NUMBER OF DATA CONVERSION CYCLES

00 1

01 4

10 8

11 16

TABLE 5. ADC RESOLUTION DATA WIDTH

0x01[3:2]

INTEGRATION TIME

(ms) RESOLUTION

00 90 16 Bits

01 5.6 12 Bits

10 0.35 8 Bits

11 0.022 4 Bits

TABLE 6. RANGE

0x01[0] FSR

0Low

1High

ISL29120

FN8314.0

May 29, 2012

Data Registers (0x02 and 0x03)

ISL29120 has two 8-bit read-only registers to hold the LSByte

and MSByte data from the ADC. The most significant byte (MSB)

is accessed at address 0x03, and the least significant byte (LSB)

is accessed at address 0x02. For 16-bit resolution, the data is

from D0 to D15; for 12-bit resolution, the data is from D0 to D11;

for 8-bit resolution, the data is from D0 to D7. The registers are

refreshed after every conversion cycle.

Interrupt Threshold Registers

Registers 0x04 and 0x05 set the low (LO) threshold for the

interrupt pin and the interrupt flag. Register 0x04 is the LSByte

and 0x05 is the MSByte. By default, the Interrupt threshold LO is

00 hex for both LSByte and MSByte.

Registers 0x06 and 0x07 set the high (HI) threshold for the

interrupt pin and the interrupt flag. Register 0x06 is the LSByte

and 0x07 is the MSByte. By default, the Interrupt threshold HI is

0xFF for both LSByte and MSByte.

Note that there is only one set of threshold registers as ISL29120

performs R, G and B conversions sequentially. If different

thresholds are required for each color, then these threshold

registers must be re-configured prior to issuing a convert start

command. If a common threshold setting for the R, G and B is

desired then the threshold register can be initialized at power-up.

Interrupt threshold registers should be programmed

appropriately for the selected ADC conversion resolution. For

example, for 12-bit mode, only the corresponding 12 bits of the

threshold registers must be programmed and the remaining bits

should be set to zero.

Interrupt Function

An interrupt event (IFLG) is indicated by 0x00[2]. The user must

clear this bit during the device initialization. The ISL29120 will

issue an interrupt indication by setting the IFLG bit if the count in

window in interrupt threshold registers. Read Register 0x00 to

clear the interrupt flag. Interrupt flags should also be cleared

following a interrupt threshold configuration change.

An Interrupt persistency 0x01[1:0] option is available for interrupt

event control for the RGB ambient light measurement. Persistency

requires x-in-a-row interrupt flags before the INT

pin is driven low.

The user must read Register 0x0 to clear the Interrupt.

Noise/Flicker Rejection

Integrating ADC’s provide excellent flicker/noise-rejection for

periodic sources whose frequency is an integer multiple of the

conversion rate. For instance, a 60Hz AC unwanted signal’s sum

from 0ms to k*16.66ms (k = 1,2...k

) is zero. Similarly, setting

the device’s integration time to be an integer multiple of the

periodic noise signal significantly improves the light sensor

output signal in the presence of noise.

Typical Application Circuit

A typical application for the ISL29120 is shown in Figure 6. The

ISL29120’s I

C address is internally hardwired as 1000110x.

The device can be connected to a system’s I

C bus with other I

compliant devices.

Suggested PCB Footprint

It is important that users check the “Surface Mount Assembly

Guidelines for Optical Dual FlatPack No Lead (ODFN) Package”

before starting ODFN product board mounting.

http://internal.intersil.com/content/dam/Intersil/documents/tb

47/tb477.pdf

PCB Layout Considerations

The ISL29120 is relatively insensitive to PCB layout. There are

only a few considerations that will ensure best performance.

Route the supply and I

C traces away from sources of digital

switching noise. Use a 1µF power-supply decoupling capacitors

close to the device. A series resistor in the power supply to isolate

switching noise elsewhere in the system is recommended. The

499kΩ resistor should be placed close to the device and away from

any noise sources.

Soldering Considerations

Convection heating is recommended for reflow soldering;

direct-infrared heating is not recommended. The plastic ODFN

package does not require a custom reflow soldering profile, and

is qualified to +260°C. A standard reflow soldering profile with a

+260°C maximum is recommended.

RGB Spectral Sensitivity

Typical spectral response of the ISL29120’s Red, Green and Blue

channels is shown in Figure 2. It should be observed that there is

a considerable cross-spectral sensitivity among three colors. In

addition, all three channels have a strong sensitivity to light in

infra-red spectrum.

It is therefore imperative that the a color sense system-based on

ISL29120 be calibrated for the desired application using a

mathematical model to compensate for the cross-spectral

coupling between the Red, Green and Blue channels.

For operation in infra-red rich environments, such as sunlight or

incandescent lighting, use of an external Infrared filter is required

for meaningful spectral color sensing.

TABLE 7. DATA REGISTERS

ADDRESS CONTENTS

0x02 D0 is LSB for 4, 8, 12 or 16-bit resolution; D3 is MSB for

4-bit resolution; D7 is MSB for 8-bit resolution

0x03 D15 is MSB for 16-bit resolution; D11 is MSB for 12-bit

resolution

FIGURE 6. ISL29120 TYPICAL APPLICATION CIRCUIT

VDD_PULLUP

SMBMaster

INT

SDA

SCL

INT

SDA

SCL

VDD

GND

REXT

499kΩ

1µF

ISL29120

PULL-UP RESISTORS

2.7kΩ TO 10kΩ

100Ω

P1-P3 P4-P6 P7-P8

ISL29120IROZ-T7

Mfr. #:

Buy ISL29120IROZ-T7

Manufacturer:

Renesas / Intersil

Description:

Light to Digital Converters Light to Digtl Sensr IC

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ISL29120IROZ-T7