January 1996
NDP603AL / NDB603AL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
______________________________________________________________________________
Absolute Maximum Ratings T
C
= 25°C unless otherwise noted
Symbol Parameter NDP603AL NDB603AL Units
V
DSS
Drain-Source Voltage 30 V
V
GSS
Gate-Source Voltage - Continuous ± 20 V
I
D
Drain Current - Continuous 25 (Note 1) A
- Pulsed 100
P
D
Total Power Dissipation @ T
C
= 25°C 50 W
Derate above 25°C 0.4 W/°C
T
J
,T
STG
Operating and Storage Temperature Range -65 to 175 °C
T
L
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
275 °C
THERMAL CHARACTERISTICS
R
θ
JC
Thermal Resistance, Junction-to-Case 2.5 °C/W
R
θ
JA
Thermal Resistance, Junction-to-Ambient 62.5 °C/W
NDP603AL.SAM
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
DC/DC converters and high efficiency switching circuits
where fast switching, low in-line power loss, and
resistance to transients are needed.
25A, 30V. R
DS(ON)
= 0.022Ω @ V
GS
=10V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low R
DS(ON)
.
175°C maximum junction temperature rating.
S
D
G
© 1997 Fairchild Semiconductor Corporation