MMM-3036-TSD Datasheet MMM-3036-TSD | P4-P6

Block Diagram

DQS0

DM0

/DQS0

/CS0

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS1

DM1

/DQS1

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS2

DM2

/DQS2

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS3

DM3

/DQS3

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS4

DM4

/DQS4

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS5

DM5

/DQS5

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS6

DM6

/DQS6

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS7

DM7

/DQS7

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ 0

DQ 1

DQ 2

DQ 3

DQ 4

DQ 5

DQ 6

DQ 7

DQ 8

DQ 9

DQ 10

DQ 11

DQ 12

DQ 13

DQ 14

DQ 15

DQ 16

DQ 17

DQ 18

DQ 19

DQ 20

DQ 21

DQ 22

DQ 23

DQ 24

DQ 25

DQ 26

DQ 27

DQ 28

DQ 29

DQ 30

DQ 31

DQ 32

DQ 33

DQ 34

DQ 35

DQ 36

DQ 37

DQ 38

DQ 39

VDDSPD

VDD/VDDQ

VREF

VSS

EEPROM

U1~U8

SDA

SCL

SA0 SA1

EEPROM

CK0,/CK0

A0~A13

BA0~BA2

CKE0

/RAS

/CAS

/WE

ODT0

U1~U8

CK1,/CK1

4 loads

Note:

1.DQ,DM,DQS & /DQS resistors :22 Ohms±5%

2.Bx,Ax,CKEx,ODTx,CSx,/RAS,

/CAS&/WEresistors :3 Ohms±5%

DQ 40

DQ 41

DQ 42

DQ 43

DQ 44

DQ 45

DQ 46

DQ 47

DQ 48

DQ 49

DQ 50

DQ 51

DQ 52

DQ 53

DQ 54

DQ 55

DQ 56

DQ 57

DQ 58

DQ 59

DQ 60

DQ 61

DQ 62

DQ 63

A0 A1 A2

4 loads

This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either

expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes

in specifications at any time without prior notice.

Absolute Maximum DC Ratings

Parameter Symbol Value Unit Notes

Voltage on VDD relative to Vss VDD -1.0 ~ 2.3 V 1

Voltage on VDDQ pin relative to Vss VDDQ -0.5 ~ 2.3 V 1

Voltage on VDDL pin relative to Vss VDDL -0.5 ~ 2.3 V 1

Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 2.3 V 1

Storage temperature TSTG -55~+100 °C 1,2

Note:

1.Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the

stress rating only and functional operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the

measurement conditions, please refer to JESD51-2 standard.

AC & DC Operating Conditions

Recommended DC operating conditions (SSTL –1.8)

Parameter Symbol

Rating

Unit Notes

Min Typ. Max

Supply voltage VDD 1.7 1.8 1.9 V

Supply voltage for DLL VDDL 1.7 1.8 1.9 V 4

Supply voltage for Output VDDQ 1.7 1.8 1.9 V 4

I/O Reference voltage VREF 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V 1,2

I/O Termination voltage VTT VREF-0.04 VREF VREF+0.04 V 3

DC Input logic high VIH(DC) VREF+0.125 - VDDQ+0.3 V

DC Input logic low VIL(DC) -0.3 - VREF-0.125 V

Note:

There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all

conditions VDDQ must be less than or equal to VDD.

1.The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the

value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track

variations in VDDQ.

2.Peak to peak AC noise on VREF may not exceed +/-2% VREF (DC).

3.VTT of transmitting device must track VREF of receiving device.

4.AC parameters are measured with VDD, VDDQ and VDDDL tied together.

Operating Temperature Condition

Parameter Symbol Rating Unit Note

Operating Temperature TOPER 0 to 85 °C 1,2

Note:

1.Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the

measurement conditions, please refer to JESD51.2 standard.

2. At 0 - 85°C, operation temperature range are the temperature which all DRAM specification will be supported.

IDD Specification parameters Definition

( IDD values are for full operating range of voltage and Temperature)

Parameter Symbol Max. Unit Note

Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),

tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD0 280 mA

Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 4, CL =

CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =

tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus

inputs are SWITCHING; Data pattern is same as IDD4W

IDD1 320 mA

Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW;

Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

IDD2P 80 mA

Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,

CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

IDD2Q 152 mA

Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is

HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

IDD2N 176 mA

Active power - down current; All banks open; tCK

= tCK(IDD); CKE is LOW; Other control and address

bus inputs are STABLE; Data bus inputs are

FLOATING

Fast PDN Exit MRS(12) = 0mA

IDD3P-F 144

Slow PDN Exit MRS(12) = 1mA IDD3P-S 136

Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD),

tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control

and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD3N 240 mA

Operating burst read current; All banks open, Continuous burst reads, IOUT =

0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =

tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs

are SWITCHING; Data pattern is same as IDD4W

IDD4R 520 mA

Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL

= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is

HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING IDD4R

IDD4W 440 mA

Burst Auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)

interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD5 680 mA

Self refresh current; CK and CK\ at 0V; CKE ≒ 0.2V; Other control and address

bus inputs are FLOATING; Data bus inputs are FLOATING

IDD6 80 mA

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =tCK(IDD), tRC = tRC(IDD),

tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Address bus inputs are STABLE during Deselects; Data pattern is same

as IDD4R; Refer to the following page for detailed timing conditions

IDD7 1000 mA

Note: 1. Module IDD was calculated on the specific brand DRAM(3Xnm) component IDD and can be differently

measured according to DQ loading capacitor.

P1-P3 P4-P6 P7-P9 P10-P11

MMM-3036-TSD

Mfr. #:

Buy MMM-3036-TSD

Manufacturer:

Terasic Technologies

Description:

Programmable Logic IC Development Tools DDR2-667 1GB 200 PIN SO-DIMM

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

MMM-3036-TSD