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AS7C1026C-15TIN

P1-P3P4-P6P7-P9
AS7C1026C
12/5/06, v 1.0 Alliance Memory P. 4 of 9
®
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read waveform 2 (OE, CE, UB, LB controlled)
3,6,8,9
Read cycle (over the operating range)
3,9
Parameter Symbol
AS7C1026C-15
Unit NotesMin Max
Read cycle time t
RC
15 – ns
Address access time t
AA
– 15 ns 3
Chip enable (CE
) access time t
ACE
– 15 ns 3
Output enable (OE
) access time t
OE
– 7 ns
Output hold from address change t
OH
4 – ns 5
CE
low to output in low Z t
CLZ
4 – ns 4, 5
CE
high to output in high Z t
CHZ
– 6 ns 4, 5
OE
low to output in low Z t
OLZ
0 – ns 4, 5
Byte select access time t
BA
– 7 ns
Byte select Low to low Z t
BLZ
0 – ns 4, 5
Byte select High to high Z t
BHZ
– 6 ns 4, 5
OE
high to output in high Z t
OHZ
– 6 ns 4, 5
Power up time t
PU
0 – ns 4, 5
Power down time t
PD
– 12 ns 4, 5
Undefined output/don’t careFalling inputRising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data validPrevious data valid
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data
IN
AS7C1026C
12/5/06, v 1.0 Alliance Memory P. 5 of 9
®
Write waveform 1 (WE controlled)
11
Write cycle (over the operating range)
11
Parameter Symbol
AS7C1026C-15
Unit NotesMin Max
Write cycle time t
WC
15 – ns
Chip enable (CE
) to write end t
CW
9 – ns
Address setup to write end t
AW
9 – ns
Address setup time t
AS
0 – ns
Write pulse width t
WP
9 – ns
Write recovery time t
WR
0 – ns
Address hold from end of write t
AH
0 – ns
Data valid to write end t
DW
7 – ns
Data hold time t
DH
0 – ns 5
Write enable to output in high Z t
WZ
– 6 ns 4, 5
Output active from write end t
OW
1 – ns 4, 5
Byte select low to end of write t
BW
9 – ns
Address
CE
LB, UB
WE
Data
IN
Data
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data undefined
high Z
Data valid
t
AH
AS7C1026C
12/5/06, v 1.0 Alliance Memory P. 6 of 9
®
Write waveform 2 (CE controlled)
11
AC test conditions
Notes:
1 During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4 These parameters are specified with C
L
= 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6WE
is high for read cycle.
7CE
and OE are low for read cycle.
8 Address is valid prior to or coincident with CE
transition low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data
OUT
Data undefined
high Z high Z
t
AS
t
AW
Data valid
t
CLZ
t
AH
168
Ω
Thevenin Equivalent:
D
OUT
+1.728 V
255
Ω
C
13
480
Ω
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
3 ns
D
OUT
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 3 ns. See Figure A.
– Input and output timing reference levels: 1.5
P1-P3P4-P6P7-P9

AS7C1026C-15TIN

Mfr. #:
Buy AS7C1026C-15TIN
Manufacturer:
Alliance Memory
Description:
SRAM 1M, 5V, 15ns FAST 64K x 16 Asynch SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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