LTC1454CS#PBF

7
LTC1454/LTC1454L
DEFI ITIO S
UU
LSB = (V
FS
– V
OS
)/(2
n
– 1) = (V
FS
– V
OS
)/4095
Nominal LSBs:
LTC1454 LSB = 4.095V/4095 = 1mV
LTC1454L LSB = 2.5V/4095 = 0.610mV
Integral Nonlinearity (INL): End-point INL is the maxi-
mum deviation from a straight line passing through the
end-points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset speci-
fication. The INL error at a given input code is calculated
as follows:
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(Code/4095)]/LSB
V
OUT
= The output voltage of the DAC measured at
the given input code
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal 1LSB change
between any two adjacent codes. The DNL error between
any two codes is calculated as follows:
DNL = (V
OUT
– LSB)/LSB
V
OUT
= The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Resolution (n): Resolution is defined as the number of
digital input bits, n. It defines the number of DAC output
states (2
n
) that divide the full-scale range. The resolution
does not imply linearity.
Full-Scale Voltage (V
FS
): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (V
OS
): The theoretical voltage at the
output when the DAC is loaded with all zeros. The output
amplifier can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
DAC CODE
LTC1454/5 • F01
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
Figure 1. Effect of Negative Offset
The offset of the part is measured at the code that corre-
sponds to the maximum offset specification:
V
OS
= V
OUT
– (Code)(V
FS
)/(2
n
– 1)
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
8
LTC1454/LTC1454L
OPERATIO
U
Serial Interface
The data on the D
IN
input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one 24-bit
word, DAC A first, then DAC B. The MSB is loaded first for
each DAC. The DAC registers load the data from the shift
register when CS/LD is pulled high. The CLK is disabled
internally when CS/LD is high. Note: CLK must be low
before CS/LD is pulled low to avoid an extra internal clock
pulse.
The buffered output of the 24-bit shift register is available
on the D
OUT
pin which swings from ground to V
CC
.
Multiple LTC1454/LTC1454Ls may be daisy-chained to-
gether by connecting the D
OUT
pin to the D
IN
pin of the next
chip, while the CLK and CS/LD signals remain common to
all chips in the daisy-chain. The serial data is clocked to all
of the chips, then the CS/LD signal is pulled high to update
all of them simultaneously.
Reference
The LTC1454L has an internal reference of 1.22V with a full
scale of 2.5V (gain of 2 configuration). The LTC1454
includes an internal 2.048V reference, making 1LSB equal
to 1mV (gain of 2 configuration). When the buffer gain is
2, the external reference must be less than V
CC
/2 and be
capable of driving the 15k minimum DAC resistor ladder.
With a gain of 1 configuration the external reference must
be less than V
CC
– 1.5V.
Voltage Output
The rail-to-rail buffered output of the LTC1454 family can
source or sink 5mA when operating with a 5V supply while
pulling to within 300mV of the positive supply voltage or
ground. The output swings to within a few millivolts of
either supply rail when unloaded and has an equivalent
output resistance of 40 when driving a load to the rails.
The output can drive 1000pF without going into oscilla-
tion.
9
LTC1454/LTC1454L
Figure 2
APPLICATIONS INFORMATION
WUU
U
A Single Supply, 4-Quadrant Multiplying DAC
The LTC1454 can also be used for 4-quadrant multiplying
with an offset signal ground of 1.22V. This application is
shown in Figure 2. The inputs are connected to REFHI B or
REFHI A and have a 1.22V amplitude around a signal
ground of 1.22V. The outputs will swing from 0V to 2.44V,
as shown by the equation with the figure. Since the signal
ground is around 1.22V, REFLO is offset above ground by
using an LT1034CS8-1.2 as shown.
V
OUT B
V
CC
REFHI B
GND
REFLO
REFHI A
REFOUT
V
CC
V
OUT B
V
OUT A
V
INB
1.22V ± 1.22V
V
INA
1.22V ± 1.22V
LT1034CS8-1.2
CLK
D
IN
CS/LD
LTC1454
1454 F02
X1/X2 B
CLR
CLK
D
IN
CS/LD
D
OUT
X1/X2 A
V
OUT A
5V
0.1µF
10k
V
OA/B
=
V
IN
– V
REFLO
GAIN – 1 +1 + V
REFLO
=
V
IN
– 1.22 2.0 – 1.0 + 1.22V
()
()
()
()
D
IN
4096
D
IN
4096

LTC1454CS#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Dual 12-Bit Vout DAC
Lifecycle:
New from this manufacturer.
Delivery:
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