74ALVC574_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 8 November 2007 5 of 17
NXP Semiconductors
74ALVC574
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
Z = high-impedance OFF-state
↑ = LOW to HIGH clock transition
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When V
CC
= 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
Table 3. Function table
[1]
Operating mode Input Internal flip-flop Output
OE CP Dn Qn
Load and read register L ↑ lLL
L ↑ hHH
Load register and disable
outputs
H ↑ lLZ
H ↑ hHZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage −0.5 +4.6 V
I
IK
input clamping current V
I
<0V −50 - mA
V
I
input voltage −0.5 +4.6 V
I
OK
output clamping current V
O
>V
CC
or V
O
<0V - ±50 mA
V
O
output voltage output HIGH or LOW state
[1] [2]
−0.5 V
CC
+ 0.5 V
output 3-state −0.5 +4.6 V
power-down mode, V
CC
= 0 V
[2]
−0.5 +4.6 V
I
O
output current V
O
= 0 V to V
CC
- ±50 mA
I
CC
supply current - 100 mA
I
GND
ground current −100 - mA
T
stg
storage temperature −65 +150 °C
P
tot
total power dissipation T
amb
= −40 °C to +85 °C
[3]
- 500 mW
