NB3N501DG Datasheet NB3N501DG, NB3N501DR2G | P4-P6

NB3N501

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Table 6. DC CHARACTERISTICS V

= 3.3 V ± 10% or 5.0 V ± 5% unless otherwise noted, GND = 0 V, T

= −40°C to +85°C

Symbol

Characteristic Min Typ Max Unit

Operating Voltage at 100 MHz (with 20 MHz crystal) V

= 5 V

= 3.3 V

4.75

3.0

5.25

3.6

Power Supply Current – Inputs and outputs open, CLKOUT operating

at 100 MHz (with 20 MHz crystal) V

= 5 V

= 3.3 V

Output HIGH Voltage I

= −4 mA CMOS High V

− 0.4 V

Output HIGH Voltage I

= −25 mA TTL High 2.4 V

Output LOW Voltage I

= 25 mA 0.4 V

Input HIGH Voltage, CLK only (pin 1) (V

/ 2) + 1 V

Input LOW Voltage, CLK only (pin 1) (V

/ 2) − 1 V

Input HIGH Voltage, S0, S1 V

− 0.5 V

Input LOW Voltage, S0, S1 0.5 V

Input HIGH Voltage, OE (pin 7) 2.0 V

Input LOW Voltage, OE (pin 7) 0.8 V

Input Capacitance, S0, S1 and OE 4 pF

Output Short Circuit Current ±70 mA

RPU On Chip Pullup Resistor 270

Nominal Output Impedance 20

3. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors

should be connected from pins X1/CLK to GND and X2 to GND. The value of these capacitors is given by the following equation, where

is the specified crystal load capacitance: Crystal capacitance (pF) = (C

− 5) X 2. So, for a crystal with 16 pF load capacitance, use

two 22 pF capacitors.

Table 7. AC CHARACTERISTICS V

= 3.3 V ± 10% or 5.0 V ± 5% unless otherwise noted, GND = 0 V, T

= −40°C to +85°C

Symbol

Characteristic Min Typ Max Unit

Xtal

Crystal Input Frequency (Note 4) 5 27 MHz

CLKIN

Clock Input Frequency 2 50 MHz

OUT

Output Frequency Range f

OUTMIN

≤ f

x Multiplier ≤ f

OUTMAX

= 4.75 to 5.25 V (5.0 V ± 5%)

= 3.0 to 3.6 V (3.3 V ± 10%)

160

100

MHz

DC Output Clock Duty Cycle at V

/ 2 45 50 55 %

Output enable time, OE high to output on 50 ns

Output disable time, OE low to tri−state 50 ns

jitter

(rms)

Period Jitter (rms, 1 s)

25 ps

jitter

(pk−to−pk)

Total Period Jitter, (peak−to−peak) ±70 ps

Output rise/fall time (0.8 V to 2.0 V) (measured with 15 pF load) 1 ns

4. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors

should be connected from pins X1/CLK to GND and X2 to GND. The value of these capacitors is given by the following equation, where

is the specified crystal load capacitance: Crystal capacitance (pF) = (C

− 12) X 2. So, for a crystal with 16 pF load capacitance, use

two 8 pF capacitors.

NB3N501

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APPLICATIONS INFORMATION

High Frequency CMOS/TTL Oscillators

The NB3N501, along with a low frequency fundamental

mode crystal, can build a high frequency TTL output

oscillator. For example, a 20 MHz crystal connected to the

NB3N501 with the 5X output selected (S1 = L, S0 = H)

produces an 100 MHz CMOS/TTL output clock.

Decoupling and External Components

The NB3N501 requires a 0.01 mF decoupling capacitor to

be connected between V

and GND on pins 2 and 3. It must

be connected close to the NB3N501 to minimize lead

inductance. Control input pins can be connected to device

pins V

or GND, or to the V

and GND planes on the

board.

Series Termination Resistor

A 33 W terminating resistor can be used next to the CLK

pin for trace lengths over one inch.

Crystal Load Capacitors

The total on chip capacitance is approximately 12 pF. A

parallel resonant, fundamental mode crystal should be used.

The device crystal connections should include pads for

small capacitors from X1 to ground and from X2 to ground.

These capacitors are used to adjust the stray capacitance of

the board to match the nominally required crystal load

capacitance. Because load capacitance can only be

increased in this trimming process, it is important to keep

stray capacitance to a minimum by using very short PCB

traces (and no vias) between the crystal and device. Crystal

capacitors, if needed, must be connected from each of the

pins X1 and X2 to ground. The value (in pF) of these crystal

caps should equal (C

− 12 pF) * 2. In this equation, C

crystal load capacitance in pF. Example: For a crystal with

a 16 pF load capacitance, each crystal capacitor would be

8 pF [(16 − 12) x 2 = 8].

ORDERING INFORMATION

Device Package Shipping

†

NB3N501DG SOIC−8

(Pb−Free)

98 Units / Rail

NB3N501DR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

NB3N501

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

SEATING

PLANE

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157

C 1.35 1.75 0.053 0.069

D 0.33 0.51 0.013 0.020

G 1.27 BSC 0.050 BSC

H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010

K 0.40 1.27 0.016 0.050

M 0 8 0 8

N 0.25 0.50 0.010 0.020

S 5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) Z

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

inches

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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PUBLICATION ORDERING INFORMATION

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

NB3N501/D

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For additional information, please contact your local

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NB3N501DG

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Clock Buffer PLL CLOCK MULTIPLIER

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NB3N501DG

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