4
ATtiny11/12
1006FS–AVR–06/07
ATtiny12 Block Diagram Figure 2 on page 4. The ATtiny12 provides the following features: 1K bytes of Flash, 64
bytes EEPROM, up to six general-purpose I/O lines, 32 general-purpose working regis-
ters, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog
Timer with internal oscillator, and two software-selectable power-saving modes. The
Idle Mode stops the CPU while allowing the timer/counters and interrupt system to con-
tinue functioning. The Power-down Mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next interrupt or hardware reset. The
wake-up or interrupt on pin change features enable the ATtiny12 to be highly responsive
to external events, still featuring the lowest power consumption while in the power-down
modes.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny12 is
a powerful microcontroller that provides a highly-flexible and cost-effective solution to
many embedded control applications.
Figure 2. The ATtiny12 Block Diagram
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
HARDWARE
STACK
MCU CONTROL
REGISTER
GENERAL-
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA REGISTER
PORTB
PROGRAMMING
LOGIC
OSCILLATORS
TIMING AND
CONTROL
INTERRUPT
UNIT
MCU STATUS
REGISTER
STATUS
REGISTER
ALU
PORTB DRIVERS
PB0-PB5
VCC
GND
CONTROL
LINES
+
-
ANALOG
COMP
ARATOR
Z
8-BIT DATA BUS
EEPROM
SPI
INTERNAL
OSCILLATOR
CALIBRATED
5
ATtiny11/12
1006FS–AVR–06/07
Pin Descriptions
VCC Supply voltage pin.
GND Ground pin.
Port B (PB5..PB0) Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected
for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain
output. The port pins are tri-stated when a reset condition becomes active, even if the
clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on
reset and clock settings, as shown below.
Notes: 1. “Used” means the pin is used for reset or clock purposes.
2. “-” means the pin function is unaffected by the option.
3. Input means the pin is a port input pin.
4. On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output.
5. I/O means the pin is a port input/output pin.
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
Table 2. PB5..PB3 Functionality vs. Device Clocking Options
Device Clocking Option PB5 PB4 PB3
External Reset Enabled Used
(1)
-
(2)
-
External Reset Disabled Input
(3)
/I/O
(4)
--
External Crystal - Used Used
External Low-frequency Crystal - Used Used
External Ceramic Resonator - Used Used
External RC Oscillator - I/O
(5)
Used
External Clock - I/O Used
Internal RC Oscillator - I/O I/O
6
ATtiny11/12
1006FS–AVR–06/07
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
Register Summary ATtiny11
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
$3F SREG I T H S V N Z C page 9
$3E Reserved
$3D Reserved
$3C Reserved
$3B GIMSK - INT0 PCIE - - - - - page 33
$3A GIFR - INTF0 PCIF - - - - - page 34
$39 TIMSK - - - - - - TOIE0 - page 34
$38 TIFR - - - - - -TOV0- page 35
$37 Reserved
$36 Reserved
$35 MCUCR - -SESM- - ISC01 ISC00 page 32
$34 MCUSR - - - - - - EXTRF PORF page 28
$33 TCCR0 - - - - - CS02 CS01 CS00 page 41
$32 TCNT0 Timer/Counter0 (8 Bit) page 41
$31 Reserved
$30 Reserved
... Reserved
$22 Reserved
$21 WDTCR - - - WDTOE WDE WDP2 WDP1 WDP0 page 43
$20 Reserved
$1F Reserved
$1E Reserved
$1D Reserved
$1C Reserved
$1B Reserved
$1A Reserved
$19 Reserved
$18 PORTB - - - PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 37
$17 DDRB - - - DDB4 DDB3 DDB2 DDB1 DDB0 page 37
$16 PINB - - PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 37
$15 Reserved
... Reserved
$0A Reserved
$09 Reserved
$08 ACSR ACD - ACO ACI ACIE - ACIS1 ACIS0 page 45
Reserved
$00 Reserved

ATTINY12V-1SI

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