EL7515IY-T7

7
FN7120.2
August 10, 2007
At very low load, the MOSFET will skip pulses sometimes.
This is normal.
Current Limit
The MOSFET current limit is nominally 1.4A and guaranteed
1A. This restricts the maximum output current I
OMAX
based
on Equation 1:
where:
I
L
is the inductor peak-to-peak current ripple and is
decided by Equation 2:
D is the MOSFET turn-on ratio and is decided by
Equation 3:
•f
S
is the switching frequency
The following table gives typical values:
Component Considerations
It is recommended that C
IN
is larger than 10µF.
Theoretically, the input capacitor has a ripple current of I
L
.
Due to high-frequency noise in the circuit, the input current
ripple may exceed the theoretical value. A larger capacitor
will reduce the ripple further.
The inductor has peak and average current decided by
Equations 4 and 5:
The inductor should be chosen to be able to handle this
current. Furthermore, due to the fixed internal
compensation, it is recommended that maximum inductance
of 10µH and 15µH to be used in the 5V and 12V or higher
output voltage, respectively.
The output diode has an average current of I
O
, and peak
current the same as the inductor's peak current. A Schottky
diode is recommended and it should be able to handle those
currents.
The output voltage ripple can be calculated as Equation 6:
Where:
•C
O
is the output capacitance.
The ESR is the output capacitor ESR value.
Low ESR capacitors should be used to minimize the output
voltage ripple. Multilayer ceramic capacitors (X5R and X7R)
are preferred for the output capacitors since they have a low
ESR and small packages. Tantalum capacitors also can be
used, but they take more board space and have higher ESR.
A minimum of 22µF output capacitor is sufficient for high
output current application. For lower output current, the
output capacitor can be smaller, like 4.7µF. The capacitor
should always have enough voltage rating. In addition to the
voltage rating, the output capacitor should also be able to
handle the RMS current which is given by Equation 7:
Output Voltage
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. The current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network less than 300k is recommended.
TABLE 1. MAX CONTINUOUS OUTPUT CURRENTS
V
IN
(V)
V
O
(V)
L
(ΜH)
F
S
(kHz)
I
OMAX
(mA)
2 5 10 1000 360
2 9 10 1000 190
2 12 10 1000 140
3.3 5 10 1000 600
3.3 9 10 1000 310
3.3 12 10 1000 230
5 9 10 1000 470
5 12 10 1000 340
9 12 10 1000 630
12 15 10 100 670
I
OMAX
1
I
L
2
--------


V
IN
V
O
---------=
(EQ. 1)
I
L
V
IN
L
---------
D
f
S
-----=
(EQ. 2)
D
V
O
V
IN
V
O
------------------------=
(EQ. 3)
I
LPK
I
LAVG
I
L
2
--------+=
(EQ. 4)
I
LAVG
I
O
1D
-------------=
(EQ. 5)
V
O
I
O
D
F
S
C
O
---------------------- I
LPK
ESR+=
(EQ. 6)
I
CORMS
1 D D
I
L
2
I
LAVG
2
--------------------+
1
12
------
I
LAVG
=
(EQ. 7)
EL7515
8
FN7120.2
August 10, 2007
The boost converter output voltage is determined by the
relationship in Equation 8:
where V
FB
slightly changes with V
DD
. The curve is shown in
this data sheet.
RC Filter
The maximum voltage rating for the VDD pin is 12V and is
recommended to be about 10V for maximum efficiency to
drive the internal MOSFET. The series resistor R
4
in the RC
filter connected to V
DD
can be utilized to reduce the voltage.
If V
O
is larger than 10V, then Equation 9 shows:
where I
DD
is shown in I
DD
vs f
S
curve. Otherwise, R
4
can be
10 to 51 with C
4
= 0.1µF.
Thermal Performance
The EL7515 uses a fused-lead package, which has a
reduced
JA
of +100°C/W on a four-layer board and
+115°C/W on a two-layer board. Maximizing copper around
the ground pins will improve the thermal performance.
This chip also has internal thermal shut-down set at around
+135°C to protect the component.
Layout Considerations
The layout is very important for the converter to function
properly. Power Ground ( ) and Signal Ground ( ) should
be separated to ensure that the high pulse current in the
Power Ground never interferes with the sensitive signals
connected to Signal Ground. They should only be connected
at one point.
The trace connected to pin 8 (FB) is the most sensitive trace.
It needs to be as short as possible and in a “quiet” place,
preferably between PGND or SGND traces.
In addition, the bypass capacitor connected to the VDD pin
needs to be as close to the pin as possible.
The heat of the chip is mainly dissipated through the SGND
pin. Maximizing the copper area around it is preferable. In
addition, a solid ground plane is always helpful for the EMI
performance.
The demo board is a good example of layout based on these
principles. Please refer to the EL7515 Application Brief for
the layout. http://www.intersil.com/data/tb/tb429.pdf
V
OUT
V
FB
1
R
2
R
1
-------+



=
(EQ. 8)
R
4
V
O
10
I
DD
---------------------=
(EQ. 9)
EL7515
9
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN7120.2
August 10, 2007
EL7515
Mini SO Package Family (MSOP)
1
(N/2)
(N/2)+1
N
PLANE
SEATING
N LEADS
0.10 C
PIN #1
I.D.
E1E
b
DETAIL X
3° ±3°
GAUGE
PLANE
SEE DETAIL "X"
c
A
0.25
A2
A1
L
0.25 C A B
D
A
M
B
e
C
0.08 C A B
M
H
L1
MDP0043
MINI SO PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE NOTESMSOP8 MSOP10
A1.101.10 Max. -
A1 0.10 0.10 ±0.05 -
A2 0.86 0.86 ±0.09 -
b 0.33 0.23 +0.07/-0.08 -
c0.180.18 ±0.05 -
D 3.00 3.00 ±0.10 1, 3
E4.904.90 ±0.15 -
E1 3.00 3.00 ±0.10 2, 3
e0.650.50 Basic -
L0.550.55 ±0.15 -
L1 0.95 0.95 Basic -
N 8 10 Reference -
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.

EL7515IY-T7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Voltage Regulators EL7515IY HI EFFOOS TG
Lifecycle:
New from this manufacturer.
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