MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
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high for one clock period before the MSB of the 12-bit
conversion result is shifted out of DOUT. Varying the
analog input to CH7 will alter the sequence of bits from
DOUT. A total of 16 clock cycles is required per con-
version. All transitions of the SSTRB and DOUT outputs
typically occur 20ns after the rising edge of SCLK.
Starting a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX1280/MAX1281’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX1280/MAX1281 are compatible with SPI/QSPI
and MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI all transmit a byte and receive a byte at the
same time. Using the Typical Operating Circuit, the
simplest software interface requires only three 8-bit
transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to
clock out the 12-bit conversion result). See Figure 17
for MAX1280/MAX1281 QSPI connections.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode, so the CPU generates the serial clock. Choose a
clock frequency from 500kHz to 6.4MHz (MAX1280) or
4.8MHz (MAX1281).
1) Set up the control byte and call it TB1. TB1 should
be of the format 1XXXXXXX binary, where the Xs
denote the particular channel, selected conversion
mode, and power mode.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simultane-
ously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simultane-
ously, receive byte RB3.
6) Pull CS high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with three leading zeros and one trailing zero. The total
conversion time is a function of the serial-clock fre-
quency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 14). For bipolar input mode, the output is two’s
complement (Figure 15). Data is clocked out on the ris-
ing edge of SCLK in MSB-first format.
