4
Commercial Temperature Range
IDT72V8981 3.3V Time Slot Interchange
Digital Switch 128 x 128
is split into two 8-bit blocks—Connection Memory HIGH and Connection
Memory LOW. Each location in Connection Memory is associated with a
particular channel in an output stream so as to provide a one-to-one correspon-
dence between Connection and Data Memories. This correspondence allows
for per channel control for each TX output stream.
In Processor Mode, data output on the TX is taken from the Connection
Memory Low and originates from the microprocessor (Figure 2). Where as in
Connection Mode (Figure 1), data is read from Data Memory using the address
in Connection Memory. Data destined for a particular channel on the serial
output stream is read during the previous channel time slot to allow time for
memory access and internal parallel-to-serial conversion.
CONNECTION MODE
In Connection Mode, the addresses of input source for all output channels
are stored in the Connection Memory Low. The Connection Memory Low
locations are mapped to corresponding 8-bit x 32-channel output. The contents
of the Data Memory at the selected address are then transferred to the parallel-
to-serial converters. By having the output channel to specify the input channel
through the Connection Memory, input channels can be broadcast to several
output channels.
PROCESSOR MODE
In Processor Mode the CPU writes data to specific Connection Memory Low
locations which are to be output on the TX streams. The contents of the
Connection Memory Low are transferred to the parallel-to-serial converter one
channel before it is to be output and are transmitted each frame to the output until
it is changed by the CPU.
CONTROL
The Connection Memory High bits (Table 4) control the per-channel
functions available in the IDT72V8981. Output channels are selected into
specific modes such as: Processor mode or Connection mode and Output
Drivers Enabled or in three-state condition.
OUTPUT DRIVE ENABLE (ODE)
The ODE pin is the master three-state output control pin. If the ODE input
is held LOW all TX outputs will be placed in high impedance regardless
Connection Memory High programming. However, if ODE is HIGH, the contents
of Connection Memory High control the output state on a per-channel basis.
DELAY THROUGH THE IDT72V8981
The transfer of information from the input serial streams to the output serial
streams results in a delay through the device. The delay through the
IDT72V8981 device varies according to the combination of input and output
streams and the movement within the stream from channel to channel. Data
received on an input stream must first be stored in Data Memory before it is sent
out.
As information enters the IDT72V8981 it must first pass through an internal
serial-to-parallel converter. Likewise, before data leaves the device, it must
pass through the internal parallel-to-serial converter. This data preparation has
an effect on the channel positioning in the frame immediately following the
incoming frame—mainly, data cannot leave in the same time slot. Therefore,
information that is to be output in the same channel position as the information
is input, relative to the frame pulse, will be output in the following frame.
Whether information can be output during a following timeslot after the
information entered the IDT72V8981 depends on which RX stream the channel
information enters on and which TX stream the information leaves on. This is
caused by the order in which input stream information is placed into Data Memory
and the order in which stream information is queued for output. Table 1 shows
the allowable input/output stream combinations for the minimum two channel
delay.
SOFTWARE CONTROL
If the A5 address line input is LOW then the IDT72V8981 Internal Control
Register is addressed. If A5 input line is high, then the remaining address input
lines are used to select the 32 possible channels per input or output stream. The
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT72V8981 Data and
Connection memories. The IDT72V8981 memory mapping is illustrated in
Table 2 and Figure 3.
The data in the control register (Table 3) consists of Memory Select and
Stream Address bits, Split Memory and Processor Mode bits. In Split Memory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory as specified by the Memory Select Bits (Bits 4
and 3 of the Control Register). The Memory Select bits allow the Connection
Memory HIGH or LOW or the Data Memory to be chosen, and the Stream
Address bits define internal memory subsections corresponding to input or
output streams.
The Processor Enable bit (bit 6) places EVERY output channel on every
output stream in Processor mode; i.e., the contents of the Connection Memory
LOW (CML, see Table 5) are output on the TX output streams once every frame
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8981
behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every
Connection Memory High (CMH) locations were set to HIGH, regardless of the
actual value. If PE is LOW, then bit 2 and 0 of each Connection Memory High
location operates normally. In this case, if bit 2 of the CMH is HIGH, the associated
TX output channel is in Processor Mode. If bit 2 of the CMH is LOW, then the
contents of the CML define the source information (stream and channel) of the
time slot that is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) the output stream and channel.
5702 drw06
TX
Microprocessor
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
Receive
Serial Data
Streams
5702 drw05
RX TX
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
Figure 2. Processor ModeFigure 1. Connection Mode
FUNCTIONAL DESCRIPTION (Cont'd)
