1998 Feb 09 8
Philips Semiconductors Preliminary specification
Octal Low Side Driver (OLSD) TJA1010
Notes
1. Open load is indicated for V
o
<V
ref
in the off-state, short-circuited load is indicated for V
o
>V
ref
in the on-state.
2. Guaranteed by design.
3. Delay caused by load excluded.
I
i
input current at pins SCL and SIE V
i
=3V 20 − 60 µA
I
LI
input leakage current at pins SI,
SIE and SCl
off-state; V
i
=3V;
T
j
=85°C; V
STBY
<1V
−−5µA
R
i(STBY)
input resistance at pin STBY V
i
=1V; T
j
<85°C40−150 kΩ
I
i(STBY)
input current at pin STBY V
i
=3V 20 − 60 µA
V
STAT(L)
status LOW voltage I
STAT(L)
= 1.6 mA −−0.4 V
V
SO(L)
serial output LOW voltage I
SO
= 1.6 mA −−0.4 V
I
LO(SO)
output leakage current at pin SO
and status outputs
off-state; V
o
=5V;
V
STBY
<1V; T
j
<85°C
−−10 µA
f
clk
clock frequency −−1 MHz
t
W(SCL)
SCL positive pulse width HIGH-to-LOW transition 500 −−ns
t
d(SIE-SCL)
delay time from SIE HIGH to SCL
LOW
100 −−ns
t
su(SIE-SCL)
set-up time from SIE LOW to SCL
HIGH
250 −−ns
t
d(SCL-SO)
delay time from SCL HIGH to SO
valid
note 3 −−250 ns
t
su(SI-SCL)
set-up time from SI to falling edge
of SCL
150 −−ns
t
h(SCL-SI)
hold time from falling edge of SCL
to SI
150 −−ns
t
h(SCL-SIE)
hold time from SCL LOW to SIE
HIGH
250 −−ns
t
su(STBY)
STBY set-up time from STBY
HIGH to SIE LOW
100 −−µs
t
h(STBY)
STBY hold time from SIE HIGH to
STBY LOW
10 −−µs
t
d(STAT)
delay time for status pin enable 40 100 250 µs
T
th(otc)
threshold overtemperature control − 170 −°C
T
th(ets)
threshold emergency temperature
shutdown
− 190 −°C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
