Apacer Memory Product Specification
Features
z Double-data-rate architecture; two data transfers per clock cycle.
z The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
z Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for
capturing data at the receiver.
z DQS is edge-aligned with data for READs; center aligned with data for WRITEs.
z Differential clock inputs (CK and /CK)
z DLL aligns DQ and DQS transitions with CK transitions
z Commands entered on each positive CK edge; data and data mask referenced to both edges
of DQS.
z Data mask (DM) for write data.
z Posted /CAS by programmable additive latency for better command and data bus efficiency.
z On-Die-Termination (ODT) for better signal quality
--- Synchronous ODT
--- Dynamic ODT
--- Asynchronous ODT
z Multi Purpose Register (MPR) for temperature read out.
z ZQ calibration for DQ drive and ODT.
z Programmable Partial Array Self-Refresh (PASR)
z /RESET pin for Power-up sequence and reset function.
z SRT range:
--- Normal/extended
--- Auto/manual self-refresh
z Programmable Output driver impedance control
Description
The 78.A2GCB.AF10C is a 256MX72 DDR3 SDRAM high density SO-UDIMM. This memory module
consists of eighteen CMOS 256MX8 bits with 8 banks DDR3 synchronous DRAMs in BGA
packages and a 2K EEPROM in an 8-pin MLF package. This module is a 204-pin small outline dual
in line memory module and is intended for mounting into a connector socket. Decoupling capacitors
are mounted on the printed circuit board for each DDR3 SDRAM.
