74ALVC125_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 10 January 2008 6 of 13
NXP Semiconductors
74ALVC125
Quad buffer/line driver; 3-state
[1] Typical values are measured at T
amb
=25°C
[2] t
pd
is the same as t
PHL
and t
PLH
.
t
en
is the same as t
PZH
and t
PZL
.
t
dis
is the same as t
PHZ
and t
PLZ
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
Σ(C
L
× V
CC
2
× f
o
) = sum of the outputs
11. Waveforms
C
PD
power dissipation
capacitance
per buffer; V
I
= GND to V
CC
; V
CC
= 3.3 V
[3]
outputs HIGH or LOW state - 27 - pF
outputs 3-state - 5 - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions 40 °C to +85 °C Unit
Min Typ
[1]
Max
Measurement points are given in Table 8.
V
OL
and V
OH
are the typical output voltage levels that occur with the output load.
Fig 6. Input nA to output nY propagation delay times
mna230
t
PHL
t
PLH
V
M
V
M
nA input
nY output
GND
V
I
V
OH
V
OL
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
V
X
V
Y
1.65 V to 1.95 V 0.5V
CC
0.5V
CC
V
OL
+ 0.15 V V
OH
0.15 V
2.3 V to 2.7 V 0.5V
CC
0.5V
CC
V
OL
+ 0.15 V V
OH
0.15 V
2.7 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V
3.0 V to 3.6 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V
74ALVC125_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 10 January 2008 7 of 13
NXP Semiconductors
74ALVC125
Quad buffer/line driver; 3-state
Measurement points are given in Table 8.
V
OL
and V
OH
are the typical output voltage levels that occur with the output load.
Fig 7. Enable and disable times
mna362
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
V
I
V
OL
V
OH
V
CC
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 8. Test circuitry for switching times
V
EXT
V
CC
V
I
V
O
mna616
DUT
C
L
R
T
R
L
R
L
G
Table 9. Test data
Supply voltage Input Load V
EXT
V
I
t
r
, t
f
C
L
R
L
t
PLH
, t
PHL
t
PLZ
, t
PZL
t
PHZ
, t
PZH
1.65 V to 1.95 V V
CC
2.0 ns 30 pF 1 k open 2 × V
CC
GND
2.3 V to 2.7 V V
CC
2.0 ns 30 pF 500 open 2 × V
CC
GND
2.7 V 2.7 V 2.5 ns 50 pF 500 open 6 V GND
3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 6 V GND
74ALVC125_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 10 January 2008 8 of 13
NXP Semiconductors
74ALVC125
Quad buffer/line driver; 3-state
12. Package outline
Fig 9. Package outline SOT108-1 (SO14)
UNIT
A
max.
A
1
A
2
A
3
b
p
cD
(1)
E
(1)
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1

74ALVC125D,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers 3.3V 2 BUF/LN DVR
Lifecycle:
New from this manufacturer.
Delivery:
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