PIC24FJ32MC104 FAMILY
DS80549A-page 4 2012 Microchip Technology Inc.
5. Module: CPU
When using the Signed 32 by 16-bit Division
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Silicon Revisions
6. Module: CPU
When a previous DISI instruction is active (i.e.,
the DISICNT register is non-zero), and the value of
the DISICNT register is updated manually, the
DISICNT register Freezes and disables interrupts
permanently.
Work around
Avoid updating the DISICNT register manually.
Instead, use the DISI #n instruction with the
required value for ‘n’.
Affected Silicon Revisions
7. Module: Oscillator
Clock switch requests are not aborted if the device
enters Sleep mode during the execution of the
clock switch.
Work around
None.
Affected Silicon Revisions
A0
X
A0
X
A0
X
