LTC3588EMSE-1/-2
2
OPERATING PRINCIPLE
Refer to the block diagram within the LTC3588-1/-2
data sheet for its operating principle.
The LTC3588 is an ultralow quiescent current power
supply designed specifically for energy harvesting
and/or low current step-down applications. The part
is designed to interface directly to a piezoelectric or
alternative A/C energy source, rectify and store the
harvested energy on an external capacitor, bleed off
any excess energy via an internal shunt regulator,
and maintain a regulated output voltage by means of
a nano-power high efficiency synchronous buck reg-
ulator.
The LTC3588 has an internal full-wave bridge recti-
fier accessible via PZ1 and PZ2 that rectifies AC in-
puts such as those from a piezoelectric element. The
rectified output is stored on a capacitor at the VIN pin
and can be used as an energy reservoir for the buck
converter. The bridge is capable of carrying up to
50mA.
When the voltage on VIN crosses the UVLO rising
threshold the buck converter is enabled and charge
is transferred from the input capacitor to the output
capacitor. A wide (~1V) UVLO hysteresis window is
employed with a lower threshold approximately
200mV above the selected regulated output voltage
to prevent short cycling during buck power-up.
When the input capacitor voltage is depleted below
the UVLO falling threshold the buck converter is dis-
abled.
Two internal rails, CAP and V
IN2, are generated from
VIN and are used to drive the high side PMOS and
low side
NMOS of the buck converter, respectively.
Additionally the VIN2 rail serves as logic high for out-
put voltage select bits D0 and D1. The VIN2 rail is re-
gulated at 4.8V above GND
while the CAP rail is regu-
lated at 4.8V below VIN. These are not intended to be
used as external rails. Capacitors should be con-
nected to the CAP and V
IN2 pins to serve as energy
reservoirs for driving the buck switches.
The buck regulator uses a hysteretic voltage algo-
rithm to control the output through internal feedback
from the VOUT sense pin. The buck converter charges
an output capacitor through an inductor to a value
slightly higher than the regulation point. It does this
by ramping the inductor current up to 250mA
through an internal PMOS switch and then ramping it
down to 0mA through an internal NMOS switch.
When the buck brings the output voltage into regula-
tion the converter enters a low quiescent current
sleep state that monitors the output voltage with a
sleep comparator. During this operating mode load
current is provided by the buck output capacitor.
When the output voltage falls below the regulation
point the buck regulator wakes up and the cycle re-
peats. This hysteretic method of providing a regu-
lated output reduces losses associated with FET
switching and maintains an output at light loads. The
buck delivers a minimum of 100mA average load
current when it is switching.
A power good comparator produces a logic high ref-
erenced to VOUT on the PGOOD pin the first time the
converter reaches the programmed V
OUT, signaling
that the output is in regulation. The PGOOD pin will
remain high until V
OUT falls to 92% of the desired
regulated voltage.
