PIC18F8720T-E/PT Datasheet PIC18F8620-I/PT, PIC18F8620T-E/PT, PIC18F8720T-E/PT | P19-P21

 2010 Microchip Technology Inc. DS39583C-page 19

PIC18FXX20

3.5 Boot Block Programming

The Boot Block segment is programmed in exactly the

same manner as the ID locations (see Section 3.4).

Multi-panel writes must be disabled so that only

addresses in the range 0000h to 01FFh will be written.

The code sequence detailed in Figure 3-6 should be

used, except that the address data used in “Step 2” will

be in the range 000000h to 0001FFh.

3.6 Configuration Bits Programming

Unlike code memory, the configuration bits are

programmed a byte at a time. The “Table Write, Begin

Programming” 4-bit command (1111) is used, but only

8 bits of the following 16-bit payload will be written. The

LSB of the payload will be written to even addresses,

and the MSB will be written to odd addresses. The

code sequence to program two consecutive

configuration locations is shown in Figure 3-7.

TABLE 3-7: SET ADDRESS POINTER TO CONFIGURATION LOCATION

FIGURE 3-10: CONFIGURATION PROGRAMMING FLOW

4-Bit

Command

Data Payload Core Instruction

Step 1: Direct access to config memory.

0000

8E A6

8C A6

BSF EECON1, EEPGD

BSF EECON1, CFGS

Step 2: Position the program counter

(1)

0000

EF 00

F8 00

GOTO 100000h

Step 3

(2)

: Set Table Pointer for config byte to be written. Write even/odd addresses.

0000

1111

0000

1111

0000

0E 30

6E F8

0E 00

6E F7

0E 00

6E F6

00 00

2A F6

00 00

MOVLW 30h

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPRTH

MOVLW 00h

MOVWF TBLPTRL

Load 2 bytes and start programming

NOP - hold SCLK high for time P9

INCF TBLPTRL

Load 2 bytes and start programming

NOP - hold SCLK high for time P9

Note 1: If the code protection bits are programmed while the program counter resides in the same block, then the interaction of

code protection logic may prevent further table write. To avoid this situation, move the program counter outside the code

protection area (e.g., GOTO 100000h).

2: Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration

bits. Always write all the configuration bits before enabling the write protection for configuration bits.

Load Even

Configuration

Start

Program

MSB

Done

Delay P9 Time

for Write

Delay P9 Time

for Write

LSB

Load Odd

Configuration

Address

Done

Start

PIC18FXX20

DS39583C-page 20  2010 Microchip Technology Inc.

4.0 READING THE DEVICE

4.1 Read Code Memory, ID Locations,

and Configuration Bits

Code memory is accessed one byte at a time via the

4-bit command, ‘1001’ (Table Read, post-increment).

The contents of memory pointed to by the Table Pointer

(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the

Table Latch and then serially output on SDATA.

The 4-bit command is shifted in LSb first. The Table

Read is executed during the next 8 clocks, then shifted

out on SDATA during the last 8 clocks, LSb to MSb. A

delay of P6 must be introduced after the falling edge of

the 8th SCLK of the operand to allow SDATA to

transition from an input to an output. During this time,

SCLK must be held low (see Figure 4-1). This operation

also increments the Table Pointer by one, pointing to the

next byte in code memory for the next read.

This technique will work to read any memory in the

000000h to 3FFFFFh address space, so it also applies

to the reading of the ID and Configuration registers.

TABLE 4-1: READ CODE MEMORY SEQUENCE

FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)

4-Bit

Command

Data Payload Core Instruction

Step 1: Set Table Pointer.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW Addr[21:16]

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 2: Read memory into Table Latch and then shift out on SDATA, LSb to MSb.

1001 00 00 TBLRD *+

1234

SCLK

SDATA

SDATA = Input

Shift Data Out

SDATA = Output

5678

1234

P5A

10 11 13 15 161412

Fetch Next 4-bit Command

1001

SDATA = Input

LSb

MSb

1234

nnnn

P14

 2010 Microchip Technology Inc. DS39583C-page 21

PIC18FXX20

4.2 Verify Code Memory and ID

locations

The verify step involves reading back the code memory

space and comparing against the copy held in the

programmer’s buffer. Memory reads occur a single byte

at a time, so two bytes must be read to compare

against the word in the programmer’s buffer. Refer to

Section 4.1 for implementation details of reading code

memory.

The Table Pointer must be manually set to 200000h

(base address of the ID locations), once the code

memory has been verified. The post-increment feature

of the Table Read 4-bit command may not be used to

increment the Table Pointer beyond the code memory

space. In a 32-Kbyte device, for example, a

post-increment read of address 7FFFh will wrap the

Table Pointer back to 0000h, rather than point to

unimplemented address 8000h.

FIGURE 4-2: VERIFY CODE MEMORY FLOW

Read Low Byte

Read High byte

Does

Word = Expect

Data?

Failure,

Report

Error

All

Code Memory

Verified?

Yes

Set Pointer = 0

Start

Set Pointer = 200000h

Yes

Read Low Byte

Read High byte

Does

Word = Expect

Data?

Failure,

Report

Error

All

ID Locations

Verified?

Yes

Done

Yes

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P40

PIC18F8720T-E/PT

Mfr. #:

Buy PIC18F8720T-E/PT

Manufacturer:

Microchip Technology

Description:

8-bit Microcontrollers - MCU 25MHz 128KB Flash

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

PIC18F8720T-E/PT

PIC18F8720T-E/PT

Products related to this Datasheet