EL6204CWZ-T7

EL6204
10
FN7219.3
October 28, 2015
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Here, V
SUP
is the supply voltage. Figures 24 and 25 provide a
convenient way to see if the device will overheat. The maximum
safe power dissipation can be found graphically, based on the
package type and the ambient temperature. By using Equation 3
,
it is a simple matter to see if P
D
exceeds the device's power
derating curve. To ensure proper operation, it is important to
observe the recommended derating curve shown in Figures 24
and 25. A flex circuit may have a higher
JA
and lower power
dissipation would then be required.
FIGURE 24. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
0.6
0.5
0.4
0.3
0.2
0.1
0
0 255075100125150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
85
PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
488mW
6
-
P
i
n
S
O
T
-
2
3
J
A
=
+
2
5
6
°
C
/
W
FIGURE 25. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
0.6
0.5
0.4
0.3
0.2
0.1
0
0 255075100125150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
85
543mW
6
-
P
i
n
S
O
T
-
2
3
J
A
=
+
2
3
0
°
C
/
W
PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 High Effective Thermal Conductivity Test Board
EL6204
EL6204
11
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FN7219.3
October 28, 2015
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About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
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.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
October 28, 2015 FN7219.3 Added Rev History beginning with Revision 3.
Updated entire datasheet applying Intersil’s new standards.
Removed obsolete parts EL6204CW-T7 AND EL6204CW-T7A
ordering information on page 3 - updated PKG DWG from MDP0038 to P6.064A, added MSL note and part
marking note.
Added Tja and Tjc in “Thermal Information” on page 4 and corresponding notes.
Added Note 7 on page 5 to MIN and MAX in Electrical Spec Tables and corresponding note.
Changed POD MDP0038 to P6.064A
EL6204
12
FN7219.3
October 28, 2015
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EL6204
Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.60
0.08-0.20
SEE DETAIL X
(0.60)
0-3°
3 5
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW END VIEW
INDEX AREA
PIN 1
SEATING PLANE
GAUGE
0.45±0.1
(2 PLCS)
10° TYP
4
1.90
0.40 ±0.05
2.90
0.95
2.80
0.05-0.15
1.14 ±0.15
0.20 C A-B DM
(1.20)
(0.60)
(0.95)
(2.40)
0.10 C
1.45 MAX
C
B
A
D
3
3
0.20 C
(1.90)
2x
0.15 C
2x
D
0.15 C
2x
A-B
(0.25)
H
64
5
5
13
2
PLANE
Dimension is exclusive of mold flash, protrusions or gate burrs.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
Foot length is measured at reference to guage plane.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
6.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:

EL6204CWZ-T7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Laser Drivers Push-Pull Oscillator Laser Apps. IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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