MAX6305–MAX6313
5-Pin, Multiple-Input,
Programmable Reset ICs
7
The ±25nA max input leakage current allows resistors on
the order of megohms. Choose the pull-up resistor in the
divider to minimize the error due to the input leakage cur-
rent. The error term in the calculated threshold is simply:
±25nA x R1
If you choose R1 to be 1MΩ, the resulting error is
±25 x 10
-9
x 1 x 10
6
= ±25mV.
Like the V
CC
voltage monitors on the MAX6306/MAX6307/
MAX6309/MAX6310/MAX6312/MAX6313, the RST IN_
inputs (when used with a voltage divider) are designed to
ignore fast voltage transients. Increase the noise immunity
by connecting a capacitor on the order of 0.1µF between
RST IN and GND (Figure 2). This creates a single-pole
lowpass filter with a corner frequency given by:
f = (1/2π) / (R1 + R2)(R1 x R2 x C)
For example, if R1 = 1MΩ and R2 = 1.6MΩ, adding a
0.1µF capacitor from RST IN_ to ground results in a
lowpass corner frequency of f = 2.59Hz. Note that
adding capacitance to RST IN slows the circuit’s overall
response time.
__________Applications Information
Interfacing to µPs with
Bidirectional Reset Pins
Since the RESET output on the MAX6305/MAX6306/
MAX6307 is open drain, these devices interface easily
with µPs that have bidirectional reset pins, such as the
Motorola 68HC11. Connecting the µP supervisor’s
RESET output directly to the microcontroller’s RESET
pin with a single pull-up resistor allows either device to
assert reset (Figure 3).
Negative-Going V
CC
Transients
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these devices
are relatively immune to short-duration, negative-going
V
CC
transients (glitches).
The
Typical Operating Characteristics
show the
Maximum Transient Duration vs. V
CC
Reset Threshold
Overdrive, for which reset pulses are not generated.
The graph was produced using negative-going pulses,
starting at V
TH
max, and ending below the pro-
grammed reset threshold by the magnitude indicated
(reset threshold overdrive). The graph shows the maxi-
mum pulse width that a negative-going V
CC
transient
may typically have without causing a reset pulse to be
issued. As the amplitude of the transient increases (i.e.,
goes farther below the reset threshold), the maximum
allowable pulse width decreases.
RST IN_/OVRST IN are also immune to negative/positive-
going transients (see
Typical Operating Characteristics
).
A 0.1µF bypass capacitor mounted close to the RST IN_,
OVRST IN, and/or the V
CC
pin provides additional tran-
sient immunity.
Ensuring a Valid
RESET
/RESET
Output Down to V
CC
= 0V
When V
CC
falls below 1V, push/pull structured RESET/
RESET current sinking (or sourcing) capabilities
decrease drastically. High-impedance CMOS-logic
inputs connected to RESET can drift to undetermined
voltages. This presents no problem in most applica-
tions, since most µPs and other circuitry do not operate
with V
CC
below 1V. In those applications where RESET
must be valid down to 0V, adding a pull-down resistor
between RESET and ground sinks any stray leakage
Figure 2. Increasing Noise Immunity
