........................DOC #: SP-AP-0052 (Rev. AA) Page 4 of 31
34 SRC10 O, DIF 100 MHz Differential serial reference clocks.
35 SRC#10 O, DIF 100 MHz Differential serial reference clocks.
36 VDD_SRC_IO PWR 3.3V-1.05V power supply for SRC outputs.
37 CPU_STOP#/SRC5# I/O,
Dif
3.3V tolerant input for stopping CPU outputs./100 MHz Differential serial reference
clocks. The option is selected by SRC5_EN
38 PCI_STOP#/SRC5 I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs./ 100 MHz Differential serial
reference clocks.The option is selected by SRC5_EN
39 VDD_SRC PWR 3.3V Power supply for SRC PLL.
40 SRC6# O, DIF 100 MHz Differential serial reference clocks.
41 SRC6 O, DIF 100 MHz Differential serial reference clocks.
42 VSS_SRC GND Ground for outputs.
43 SRC7# O, DIF 100 MHz Differential serial reference clocks
44 SRC7 O, DIF 00 MHz Differential serial reference clocks
45 VDD_SRC_IO PWR 3.3V-1.05V power supply for SRC outputs.
46 SRC8#/CPUC2_ITP# O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
47 SRC8/CPUT2_ITP O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
48 SEL_24.576M I, PD Select 25M1_24.576M output and SRC1
0 = 25M1, M= SRC1, 1 = 24.576M
49 VDD_CPU_IO PWR 3.3V-1.05V power supply for CPU outputs.
50 CPU1# O, DIF Differential CPU clock outputs.
Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
51 CPU1 O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
52 VSS_CPU GND Ground for outputs.
53 CPU0# O, DIF Differential CPU clock outputs.
54 CPU0 O, DIF Differential CPU clock outputs.
55 VDD_CPU PWR 3.3V Power supply for CPU PLL.
56 CK_PWRGD/PWRDWN# I 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
57 FSB/TEST_MODE I 3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
58 VSS_REF GND Ground for outputs.
59 XTAL_OUT O, SE 14.318 MHz Crystal output.
60 XTAL_IN I 14.318 MHz Crystal input.
61 VDD_REF PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
62 REF0/FSC/TEST_SEL I/O 3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects
test mode if pulled to V
IHFS_C
when CK_PWRGD is asserted HIGH. Refer to DC
Electrical Specifications table for V
ILFS_C
, V
IMFS_C
, V
IHFS_C
specifications.
64-TSSOP Pin Definitions
Pin No. Name Type Description